• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.80-80
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• 2009

Recently, multiferroics have attracted much attention due to their numorous potentials. In this work, we attemped to utilize the multiferroics as an alternative material for ferroelectrics. Ferroelectric materials have been stadied to ferroelectric random access memories, however, some inevitable problems prevent it from inplementation. multiferroics shows a ferroelectricity and has low process temperature $BiFeO_3$(BFO) films have good ferroelectric properties but poor leakage characterization. Thus we tried, in this work, to adopt $HfO_2$ insulating layer for metal-ferroelectric-insulator-semiconductor(MFMIS) structure to surpress to leakage current. $BiFeO_3$(BFO) thin films were fabricared by using a sol-gel method on $HfO_2/Si$ structure. Ferroelectric BFO films on a p-type Si(100)wafer with a $HfO_2$ buffer layer have been fabricated to form a metal-ferroelectric-insulator-semiconductor (MFIS) structure. The $HfO_2$ insulator were deposited by using a sol-gel method. Then, they were carried out a rapid thermal annealing(RTA) furnace at $750\;^{\circ}C$ for 10 min in $N_2$. BFO films on the $HfO_2/Si$ structures were deposited by sol-gel method and they were crystallized rapid thermal annealing in $N_2$ atomsphere at $550\;^{\circ}C$ for 5 min. They were characterized by atomic force microscopy(AFM) and Capacitance-voltage(C-V) curve.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.112-112
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• 2009

Temperature dependence of the ferroelectric properties of poly(vinylidefluoride-trifluoroethylene) copolymer thin films are studied with various insulators such as $SrTa_2O_6$ and $La_2O_3$. Thin films of poly(vinylidene fluoridetrifluoroethylene) 75/25 copolymer were prepared by chemical solution deposition on p-Si substrate. Capacitance-voltage (C-V) and current density (J-V) behavior of the Au/P(VDF-TrFE)/Insulator/p-Si structures were studied at ($150-200\;^{\circ}C$) and dielectric constant of the each insulators were measured to be about 15 at $850\;^{\circ}C$ for 10 minutes. Memory window width at 5 V bias the MFIS(metal-ferroelectric-insulator-semiconductor) structure with as deposited films was about 0.5 V at high temperature ($200\;^{\circ}C$). And the memory window width increased as voltage increased from 1 V to 5 V.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.171-172
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• 2007

We fabricated the metal-ferroelectric-insulator-semiconductor filed-effect transistors (MFIS-FETs) using the $(Bi,La)_4Ti_3O_{12}\;and\;LaZrO_x$ thin films. The $LaZrO_x$ thin film had a equivalent oxide thickness (EOT) value of 8.7 nm. From the capacitance-voltage (C-V) measurements for an Au/$(Bi,La)_4Ti_3O_{12}/LaZrO_x$/Si MFIS capacitor, a hysteric shift with a clockwise direction was observed and the memory window width was about 1.4 V for the bias voltage sweeping of ${\pm}9V$. From drain current-gate voltage $(I_D-V_G)$ characteristics of the fabricated Fe-FETs, the obtained threshold voltage shift (memory window) was about 1 V due to ferroelectric nature of BLT film. The drain current-drain voltage $(I_D-V_D)$ characteristics of the fabricated Fe-FETs showed typical n-channel FETs current-voltage characteristics.

• 한국세라믹학회지
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• 제37권11호
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• pp.1051-1057
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• 2000

TiO$_2$와 CeO$_2$박막을 Si 위에 증착한 후 MOCVD법에 의해 PbTiO$_3$박막을 증착하여 MFIS 구조를 형성하였다. 절연층의 후열처리가 절연층 및 MFIS 구조의 전기적 특성에 미치는 영향을 관찰하기 위해 산소분위기와 $600^{\circ}C$~90$0^{\circ}C$의 온도범위에서 후 열처리를 행하였고, C-V 특성 및 누설전류 특성을 분석하였다. CeO$_2$와 TiO$_2$박막의 유전상수는 증착 직후 6.9와 15였으며, 90$0^{\circ}C$ 열처리를 행한 후 약 4.9와 8.8로 감소하였다. 누설전류밀도 역시 증착 직후 각각 7$\times$$10^{-5}$ A/$ extrm{cm}^2$와 2.5$\times$$10^{-5}$ A/$\textrm{cm}^2$에서 90$0^{\circ}C$ 열처리를 거친 후에 약 4$\times$$10^{-8}$ A/$\textrm{cm}^2$와 4$\times$$10^{-9}$ A/$\textrm{cm}^2$로 감소하였다. Ellipsometry 시뮬레이션을 통해 계산된 계면층의 두께는 90$0^{\circ}C$에서 약 115$\AA$(CeO$_2$) 및 140$\AA$(TiO$_2$)까지 증가하였다. 계면층은 MFIS 구조에서 강유전층에 인가되는 전계를 감소시켜 항전계를 증가시켰고, charge injection을 방지하여 Al/PbTiO$_3$/CeO$_2$(90$0^{\circ}C$, $O_2$)/Si 구조의 경우 $\pm$2 V~$\pm$10 V의 측정범위에서 memory window가 계속 증가하는 것을 보여주었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.433-436
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• 1999

In this paper we applied TVS(Triangular Voltage Sweep) method to calculate the mobile ionic charge densities in some ferroelectric thin films. During the measurement, the temperature of specimens were maintained at 20$0^{\circ}C$. By this method, the amount of mobile ionic charge Q$_{m}$ and mobile ionic charge density N$_{m}$ of a MFIS structure were calculated 3.5 [pC] and about 4.3$\times$10$^{11}$ [ions/cm$^2$], respectively. In order to successful TVS measurement, the gate leakage current density of films must be low 10$^{-9}$ (A/cm$^2$) order.der.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2001년도 춘계학술발표강연 및 논문개요집
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• pp.94-94
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• 2001

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.133.4-133
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• 1998

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.326-329
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• 2002

In this paper, we investigated a feasibility of cerium oxide(CeO$_2$) films as a buffer layer of MFIS(metal ferroelectric insulator semiconductor) type capacitor. CeO$_2$ layer were Prepared by two step process of a low temperature film growth and subsequent RTA (rapid thermal annealing) treatment. By app1ying an ultra thin Ce metal seed layer and N$_2$ Plasma treatment, dielectric and interface properties were improved. It means that unwanted SiO$_2$ layer generation was successfully suppressed at the interface between He buffer layer and Si substrate. The lowest lattice mismatch of CeO$_2$ film was as low as 1.76% and average surface roughness was less than 0.7 m. The Al/CeO$_2$/Si structure shows breakdown electric field of 1.2 MV/cm, dielectric constant of more than 15.1 and interface state densities as low as 1.84${\times}$10$\^$11/ cm$\^$-1/eV$\^$-1/. After N$_2$ plasma treatment, the leakage current was reduced with about 2-order.

• 한국재료학회지
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• 제10권3호
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• pp.199-203
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• 2000

세라믹 타겟인 Ta$_2$O(sub)5을 장착한 rf-마그네트론 스퍼터를 이용하여 Ta$_2$O(sub)5 완충층을 증착하고, Sr(sub)0.8Bi(sub)2.4Ta$_2$O(sbu)9 용액을 사용하여 MOD 법에 의해 SBT 막을 성장시킨 metal/ferroelectric/insulator/semiconductor (MFIS) 구조인 Pt/SBT/Ta$_2$O(sub)5/Si 구조의 Ta$_2$O(sub)5 완충층 증착시의 $O_2$유량비, Ta$_2$O(sub)5 완충층 두께에 따른 전기적 특성을 조사하였다. 그리고 Ta$_2$O(sub)5 박막의 완충층으로써의 효과를 확인하기 위해 Pt/SBT/Ta$_2$O(sub)5/Si 구조와 Pt/SBT/Si 구조의 전기적 특성을 비교하였다. Ta$_2$O(sub)5 완충층 증착시의 $O_2$유량비가 0%일 때는 전형적인 MFIS 구조의 C-V 특성을 얻지 못하였으며, 20%의 $O_2$유량비일 때 가장 큰 메모리 윈도우 값을 얻었다. 그리고 $O_2$유량비가 40%, 60%로 증가할수록 메모리 윈도우는 감소하였다. Ta$_2$O(sub)5 완충층의 두께의 변화에 대한 C-V 특성에서는 36nm의 Ta$_2$O(sub)5 두께에서 가장 큰 메모리 값을 얻었다. Pt/SBT/Si 구조의 메모리 윈도우 값과 누설전류 특성은 Pt/SBT/Ta$_2$O(sub)5/Si 구조의 값에 비해 크게 떨어졌으며, 따라서 Ta$_2$O(sub)5 막이 우수한 완충층으로써의 역할을 함을 알았다.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.133.3-133
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• 1998