• Journal of Institute of Control, Robotics and Systems
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• v.22 no.9
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• pp.705-709
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• 2016

Micro-electro-mechanical systems (MEMS) gyroscopes are widely used in various robot applications. However, these conventional gyroscopes need to vibrate the proof mass using a built-in actuator at a fixed resonance frequency to sense the Coriolis force. When a robot is not moving, the meaningless vibration of the gyroscope wastes power. In addition, this continuous vibration makes the sensor vulnerable to external sound waves with a frequency close to the proof-mass resonance frequency. In this paper, a feasibility study of a new type of gyroscope inspired by insect halteres is presented. In dipterous insects, halteres are a biological gyroscope that measures the Coriolis force. Wing muscles and halteres are mechanically linked, and the halteres oscillate simultaneously with wing beats. The vibrating haltere experiences the Coriolis force if the insect is going through a rotational motion. Inspired by this haltere structure, a gyroscope using a thin mast integrated with a robot actuation mechanism is proposed. The mast vibrates only when the robot is moving without requiring a separate actuator. The Coriolis force of the mast can be measured with an accelerometer installed at the tip of the mast. However, the signal from the accelerometer has multiple frequency components and also can be highly corrupted with noise, such that raw data are not meaningful. This paper also presents a suitable signal processing technique using the amplitude modulation method. The feasibility of the proposed haltere-inspired gyroscope is also experimentally evaluated.

• Journal of Advanced Navigation Technology
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• v.16 no.6
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• pp.927-934
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• 2012

In this paper, we present relative positioning algorithm for moving land vehicle using GPS, MEMS IMU and B-CDMA module. This algorithm does not calculate precise absolute position but calculates relative position directly, so additional infrastructure and I2V communication device are not required. Proposed algorithm has several steps. Firstly, unbiased relative position is calculated using pseudorange difference between two vehicles. Simultaneously, the algorithm estimates position of each vehicle using GPS/INS integration. Secondly, proposed algorithm performs filtering and finally estimates relative position and relative velocity. Using proposed algorithm, we can obtain more precise relative position for moving land vehicles with short time interval as IMU sensor has. The simulation is performed to evaluate this algorithm and the several field tests are performed with real time program and miniature vehicles for verifying performance of proposed algorithm.

• Journal of the Korean Geosynthetics Society
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• v.18 no.4
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• pp.107-114
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• 2019

In this paper, the P-wave multiple detection system for the fast and accurate earthquake early warning nearby the epicenter was developed. The developed systems were installed in five selected public buildings for the validation. During the monitoring, a magnitude 2.3 earthquake occurred in Pohang on 26 September 2019. P-wave initial detection algorithms were operated in three out of four systems installed in Pohang area and recorded as seismic events. At the nearest station, 5.5 km from the epicenter, P-wave signal was detected 1.2 seconds after the earthquake, and S-wave was reached 1.02 seconds after the P-wave reached, providing some alarm time. The maximum accelerations recorded in three different stations were 6.28 gal, 6.1 gal, and 5.3 gal, respectively. The alarm algorithm did not work, due to the high threshold of the maximum ground acceleration (25.1 gal) to operate it. If continuous monitoring and analysis are to be carried out in the future, the developed system could use a highly effective earthquake warning system suitable for the domestic situation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.149-158
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• 2005

This paper describes design, fabrication, and application of the silicon based temperature controllable micro reactor. In order to achieve fast temperature variation and low energy consumption, reaction chamber of the micro reactor was thermally isolated by etching the highly conductive silicon around the reaction chamber. Compared with the model not having thermally isolated structure, the thermally isolated micro reactor showed enhanced thermal performances such as fast temperature variation and low energy consumption. The performance enhancements of the micro reactor due to etched holes were verified by thermal experiment and numerical analysis. Regarding to 42 percents reduction of the thermal mass achieved by the etched holes, approximately 4 times faster thermal variation and 5 times smaller energy consumption were acquired. The total size of the fabricated micro reactor was $37{\times}30{\times}1mm^{3}$. Microchannel and reaction chamber were formed on the silicon substrate. The openings of channel and chamber were covered by the glass substrate. The Pt electrodes for heater and sensor are fabricated on the backside of silicon substrate below the reaction chamber. The dimension of channel cross section was $200{\times}100{\mu}m^{2}$. The volume of reaction chamber was $4{\mu}l$. The temperature of the micro reactor was controlled and measured simultaneously with NI DAQ PCI-MIO-16E-l board and LabVIEW program. Finally, the fabricated micro reactor and the temperature control system were applied to the thermal denaturation and the trypsin digestion of protein. BSA(bovine serum albumin) was chosen for the test sample. It was successfully shown that BSA was successfully denatured at $75^{\circ}C$ for 1 min and digested by trypsin at $37^{\circ}C$ for 10 min.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.