• Food Science and Preservation
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• v.7 no.4
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• pp.395-402
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• 2000

To enlarge application field of electrolyzed acid-water(EAW) on food industry, the changes of EAW properties by storage conditions and heating were investigatet. It was showed that storing EAW in closed container is mon effective to keep up the oxidation-reduction potentials(ORP), hyperchloride content and pH than stored in opened ones. ORP of EAW stored in closed container could be kept mon than 1 month as 1,150 mV levels. Ruing heating from 2$0^{\circ}C$ to 95$^{\circ}C$, ORP was increased to 1,150 mV levels at 95$^{\circ}C$ after gradual decrease to 5$0^{\circ}C$. Tyrosinase activity was decreased approximately to 26%~35% in EAW having a 950 mV~1,140 mV ORP. Also it was confirmed that EAW has anti-browning effect as sliced apple and potato, and their juices treated with EAW had conspicous difference in their $\Delta$E value. 12 kinds of pesticides such as aldrine, capful diazinon, diedrin, $\alpha$-endosulfan $\beta$-endosulfan, endosulfan sulfate, endrin, $\alpha$-BHC, o,p'-DDT, procymidone, PCNB added in EAW were recovered from ND~73.6% comparing to ones added in distilled water. The recovered amounts of pesticides, procymidone and diazinon in lettuce after soaking in EAW were 1.12 ppm and ND, compared with those of amounts soaked in distilled water were 3.67 ppm and 3.05 ppm respectively. So, it seems that EAW has potentials to promote the degradation of pesticides.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of the Korea Society for Simulation
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• v.24 no.3
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• pp.55-60
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• 2015

This paper presents an SBA (simulation-based acquisition) effectiveness analysis environment using the RUP (Relational Unified Process) model. The RUP model has 4 phases which cover the whole development steps such as requirement analysis, design, development and test. By applying the RUP model, SW development can be represented with the iterations of developments for each phase. Such a characteristics of the model would make the model suitable for defense acquisition. In this paper, we show the relation between the RUP model and V process model, which is the foundation for defense acquisition. In order to show how the model could be applied to SBA effectiveness analysis, graphical user interfaces for the analysis are presented at the end of the paper.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.2
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• pp.330-337
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• 2018

This paper proposes a technique to analyze the flatness characteristics of the attenuator at 10Hz to $50\text\tiny{MHz}$ on the basis of $1\text\tiny{kHz}$ using a Thermal Voltage Converter and AC measurement standard. In the proposed technique, the input voltage of the attenuator for each measuring frequency is supplied at the same rate as $1\text\tiny{kHz}$ using TVC, and the flatness characteristics of the attenuator are analyzed by the voltage variation indicated in the AC measurement standard. The results of the analysis of the attenuator flatness characteristics show that the maximum uncertainty of $866{\mu}V/V$ can be measured from $10\text\tiny{dB}$ to $70\text\tiny{dB}$ and the uncertainty is reduced by about 37% compared to $2.31\text\tiny{mV}$/V using the network measurement method. The improved attenuator flatness characteristic values can be applied to the frequency flatness calibration from 2.2V to 2.2mV at the low voltage of the AC measurement standard.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.11 no.1
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• pp.14-23
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• 1997

In this paper, the results of the measurement and analysis of extremely low frequency(ELF) electric field in the vicinity of 154[kV] overhead transmission lines have been described. The planar-type electric field sensor has been fabricated by three dimensional structure with special consideration of taking the power frequency and lower components. The calibration experiments have been carried out according to the procedures of IEEE recommendation. The electric field measuring system has the frequency bandwidth of 7[Hz] to 2.7[MHz] and the response sensitivity of 0.094[mV/V/m]. Also the practical measurements of electric field under an 154[kV] double circuit overhead transmission lines have been made and analyzed. It was known that the lateral electric field profiles under an 154[kV] double circuit overhead transmission lines show the asymmetrical distributions owing to the environmental metal frame structures and their maximum electric field magnitude is less than 3[kV/m]. It can be concluded that the measured results of the electric fields satisfy with all limits or guidelines of the various authorized international institutes' recommendations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.6
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• pp.25-32
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• 2011

This paper proposes high efficiency current-mode DC-DC buck converter that are suitable for portable devices. The current-mode DC-DC buck converter using adjustable Dead-time control method improves the power efficiency 2~5%. The buck converter has been implemented with a standard 0.35${\mu}m$ CMOS process. The size of this chip is 0.97$mm^2$. The input range of the fabricated DC-DC buck converter is 2.5V~3.3V, and the output is 1.8V. The maximum loading current of the converter is 500mA and the peak efficiency is 93% at 200mA loads.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.95-102
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• 2001

Nano-scale gate length MOSFET devices require extremely shallow source/drain eftension region with junction depth of 20∼30nm. In this work, 20nm $n^{+}$-p junctions that are realized by using this $As_{2}^{+}$ low energy ($\leq$10keV) implantation show the lower sheet resistance of the $1.0k\Omega$/$\square$ after rapid thermal annealing process. The $As_{2}^{+}$ implantation and RTA process make it possible to fabricate the nano-scale NMOSFET of gate length of 70nm. $As_{2}^{+}$ 5 keV NMOSFET shows a small threshold voltage roll-off of 60mV and a DIBL effect of 87.2mV at 100nm gate length devices. The electrical characteristics of the fabricated devices with the heavily doped and abrupt $n^{+}$-p junctions ($N_{D}$〉$10^{20}$$cm^{-3}$, $X_{j}$$\leq$20nm) suggest the feasibility of the nano-scale NMOSFET device fabrication using the $As_{2}^{+}$ low energy ion implantation.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.01a
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• pp.57-58
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• 2020

본 논문은 영상분할 기법 중 DeepLab V3+를 적용하여 초음파 영상속에서 특정 장기, 혹은 기관을 발견하고자한다. 그와 동시에 찾아진 Object의 area를 mIOU 기반으로 초음파 영상속에서의 DeepLab V3+의 성능을 확인하고자 한다.