• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.89-95
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• 2008

In the maritime communication, Orthogonal Frequency Division Multiplexing (OFDM) communication terminal should be operated with low power consumption, because the communication should be accomplished in the circumstance of disaster. Therefore, Low power FFT processor is required to be designed with current mode signal processing technique than digital signal processing. Current- to-Voltage Converter (IVC) is a device that converts the output current signal of FFT processor into the voltage signal. In order to lessen the power consumption of OFDM terminal, IVC should be designed with low power design technique and IVC should have wide linear region for avoiding distortion of signal voltage. To design of one-chip of the FFT LSI and IVC, IVC should have a small chip size. In this paper, we proposed the new IVC with wide linear region. We confirmed that the proposed IVC operates linearly within 0.85V to 1.4V as a function of current-mode FFT output range of -100~100[uA]. Designed IVC will contribute to realization of low-power maritime data communication using OFDM system.

• Computational Structural Engineering
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• v.10 no.4
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• pp.185-193
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• 1997

A major problem of frequency analysis in the field of low-frequencies such as building or construction vibration is the way of signal processing which is appropriate to obtain included frequency content from the finite process to be measured. Therefore, it is the aim of the investigation reported herein to develop the signal processing algorithm which is analyzed without losing the reliability of the measurements in low-frequency domain. To accomplish the research objective, it was analyzed the problems on the way of signal processing in low-frequency domain, and compared the response characteristics of FFT with those of MEM (Maximum Entropy Method) about the low-frequency of vibration. This evaluation of the response characteristics is used in determining appropriate signal processing algorithm into the low-frequency domain.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.9-15
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• 2006

In this paper, signal processing techniques for noncoherent impulse-radio-based UWB (IR-UWB) communication system are proposed to provide system implementation of low power consumption and low complexity. The proposed system adopts a simple modulation technique of OOK (on-oft-keying) and noncoherent signal detection based on signal amplitude. In particular, a technique of a novel high speed digital sampler using a stable, lower reference clock is developed to detect nano-second pulses and recover digital signals from the pulses. Also, a 32 bits Turyn code for data frame synchronization and a convolution code as FEC are applied, respectively. To verify the proposed signal processing techniques for low power, low complexity noncoherent IR-UWB system, the proposed signal processing technique is implemented in FPGA and then a short-range communication system for wireless transmission of high quality MP3 data is designed and tested.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.27 no.5
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• pp.81-88
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• 2013

A low voltage circuit breaker protects electrical equipments from over current and short faults of system by cutting the power supply. The breaker use a thermal magnetic type trip device from the past. In recent years, electronic type relays are applied due to useful functions and services. The purpose of this development is full digitalizing of relay functions of a low voltage breaker. It includes separation of current sensor from current transformer, digital signal processing, high speed relaying, and voltage measuring for power meter. The suggestions are tested and implemented by making prototype and testing its all relay functions.

• Journal of Sensor Science and Technology
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• v.30 no.2
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• pp.82-87
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• 2021

In this paper, we propose a high-speed, low-power complementary metal-oxide semiconductor (CMOS) binary image sensor featuring a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector based on a double-tail comparator. The GBT photodetector forms a structure in which the floating gate (n+ polysilicon) and body of the PMOSFET are tied, and amplifies the photocurrent generated by incident light. The double-tail comparator compares the output signal of a pixel against a reference voltage and returns a binary signal, and it exhibits improved power consumption and processing speed compared with those of a conventional two-stage comparator. The proposed sensor has the advantages of a high signal processing speed and low power consumption. The proposed CMOS binary image sensor was designed and fabricated using a standard 0.18 ㎛ CMOS process.

• ETRI Journal
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• v.31 no.6
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• pp.717-724
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• 2009

This paper describes a 1.2 V 12 b 60 MS/s CMOS analog front-end (AFE) employing low-power and flexible design techniques for image signal processing. An op-amp preset technique and programmable capacitor array scheme are used in a variable gain amplifier to reduce the power consumption with a small area of the AFE. A pipelined analog-to-digital converter with variable resolution and a clock detector provide operation flexibility with regard to resolution and speed. The AFE is fabricated in a 0.13 ${\mu}m$ CMOS process and shows a gain error of 0.68 LSB with 0.0352 dB gain steps and a differential/integral nonlinearity of 0.64/1.58 LSB. The signal-to-noise ratio of the AFE is 59.7 dB at a 60 MHz sampling frequency. The AFE occupies 1.73 $mm^2$ and dissipates 64 mW from a 1.2 V supply. Also, the performance of the proposed AFE is demonstrated by an implementation of an image signal processing platform for digital camcorders.

• Journal of the Korea Institute of Military Science and Technology
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• v.16 no.3
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• pp.382-389
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• 2013

In anti-jamming GPS receiver, adaptive signal processing techniques in which the radiation pattern of adaptive array antenna of elements may be adaptively changed used to reject interference, clutter, and jamming signals. In this paper, I describes adaptive signal processing technique using the sample matrix inversion(SMI) algorithm. This adaptive signal processing technique can be applied effectively to wideband/narrowband anti-jamming GPS receiver because it does not consider the satellite signal directions and GPS signal power level exists below the thermal noise. I also analyzed the effects of covariance matrix sample size and diagonal loading technique on the system performance of five-element circular array antenna. To attain near optimum performance, more samples required for calculation covariance matrix. Diagonal loading technique reduces the system nulling capability against low-power jamming signals, but this technique improves robustness of adaptive array antenna.

• Journal of Sensor Science and Technology
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• v.29 no.2
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• pp.82-88
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• 2020

In this paper, we propose a complementary metal-oxide semiconductor (CMOS) binary image sensor with a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector using a double-tail comparator for high-speed and low-power operations. The GBT photodetector is based on a PMOSFET tied with a floating gate (n+ polysilicon) and a body that amplifies the photocurrent generated by incident light. A double-tail comparator compares an input signal with a reference voltage and returns the output signal as either 0 or 1. The signal processing speed and power consumption of a double-tail comparator are superior over those of conventional comparator. Further, the use of a double-sampling circuit reduces the standard deviation of the output voltages. Therefore, the proposed CMOS binary image sensor using a double-tail comparator might have advantages, such as low power consumption and high signal processing speed. The proposed CMOS binary image sensor is designed and simulated using the standard 0.18 ㎛ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.127-130
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• 2000

This paper proposes a low-Power DDC(Digital Down Converters) architecture for IF(Intermediate frequency) signal processing. It is shown that concept of conventional interpolated FIR filters can be expanded to IIR filters for DDC applications. Also in the paper, power dissipations for the proposed architecture and conventional ones are estimated.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.5
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• pp.49-56
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• 2004

A low power consuming voice signal processing and control module was designed using a small $\mu$-controller for use in a totally implantable middle ear system. The module was designed that it can control the implanted system as well as process the fitting algorithm of input sound signal. In ordinary operation mode, the $\mu$-controller processes the applied sound signal for compensating the hearing loss of the patients. When the control signal is applied from the IR receiving module, the $\mu$-controller interrupts the signal processing and executes the order of the control signals such as power on/off, volume up/down. The designed module was implemented and verified the performance of the system through several experiments.