• IEMEK Journal of Embedded Systems and Applications
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• v.3 no.1
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• pp.34-41
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• 2008

There are many researches to build up ubiquitous environment by the Ubiquitous Sensor Network(USN). These applications, such as home network, health care, natural environment and agricultural areas, are implemented by an embedded system. Their fields are gradually spreading. However the power consumption in its implementation plays an important role on the surrounding environment of the wireless network. In this paper, we design low power processor based sensor node platform for agricultural applications. We also compare its some performance with existing products.

• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.255-265
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• 2009

This paper presents the acoustic noise and mechanical vibration reduction of a coreless brushless DC motor with an air dynamic bearing used in a digital lightening processor. The coreless brushless DC motor does not have a stator yoke or stator slot to remove the unbalanced force caused by the interaction between the stator yoke and the rotor magnet. An unbalanced force makes slotless brushless DC motors vibrate and mechanically noisy, and the attractive force between the magnet and the stator yoke increases power consumption. Also, when a coreless brushless DC motor is driven by a $120^{\circ}$ conduction type inverter, high frequency acoustic noise occurs because of the peak components of the phase currents caused by small phase inductance and large phase resistance. In this paper, a core-less brushless DC motor with an air dynamic bearing to remove mechanical vibration and to reduce power consumption is applied to a digital lightening processor. A $180^{\circ}$ conduction type inverter drives it to reduce high frequency acoustic noise. The applied methods are simulated and tested using a manufactured prototype motor with an air dynamic bearing. The experimental results show that a coreless brushless DC motor has characteristics of low power consumption, low mechanical vibration, and low high frequency acoustic noise.

• Journal of Advanced Engineering and Technology
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• v.5 no.4
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• ETRI Journal
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• v.30 no.3
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• pp.451-460
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• 2008

Recently, the power consumption of integrated circuits has been attracting increasing attention. Many techniques have been studied to improve the power efficiency of digital signal processing units such as fast Fourier transform (FFT) processors, which are popularly employed in both traditional research fields, such as satellite communications, and thriving consumer electronics, such as wireless communications. This paper presents solutions based on parallel architectures for high throughput and power efficient FFT cores. Different combinations of hybrid low-power techniques are exploited to reduce power consumption, such as multiplierless units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and parallel-pipelined architectures. A number of FFT cores are implemented and evaluated for their power/area performance. The results show that up to 38% and 55% power savings can be achieved by the proposed pipelined FFTs and parallel-pipelined FFTs respectively, compared to the conventional pipelined FFT processor architectures.

• Electronics and Telecommunications Trends
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• v.33 no.5
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• pp.121-134
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• 2018

The Von Neumann based architecture of the modern computer has dominated the computing industry for the past 50 years, sparking the digital revolution and propelling us into today's information age. Recent research focus and market trends have shown significant effort toward the advancement and application of artificial intelligence technologies. Although artificial intelligence has been studied for decades since the Turing machine was first introduced, the field has recently emerged into the spotlight thanks to remarkable milestones such as AlexNet-CNN and Alpha-Go, whose neural-network based deep learning methods have achieved a ground-breaking performance superior to existing recognition, classification, and decision algorithms. Unprecedented results in a wide variety of applications (drones, autonomous driving, robots, stock markets, computer vision, voice, and so on) have signaled the beginning of a golden age for artificial intelligence after 40 years of relative dormancy. Algorithmic research continues to progress at a breath-taking pace as evidenced by the rate of new neural networks being announced. However, traditional Von Neumann based architectures have proven to be inadequate in terms of computation power, and inherently inefficient in their processing of vastly parallel computations, which is a characteristic of deep neural networks. Consequently, global conglomerates such as Intel, Huawei, and Google, as well as large domestic corporations and fabless companies are developing dedicated semiconductor chips customized for artificial intelligence computations. The AI Processor Research Laboratory at ETRI is focusing on the research and development of super low-power AI processor chips. In this article, we present the current trends in computation platform, parallel processing, AI processor, and super-threaded AI processor research being conducted at ETRI.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.437-443
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• 2007

In this paper, we propose the power-aware test framework for Network-on-Chip, which is based on embedded processor and on-chip network. First, the possibility of using embedded processor and on-chip network isintroduced and evaluated with benchmark system to test the other embeddedcores. And second, a new generation method of test pattern is presented to reduce the power consumption of on-chip network, which is called don't care mapping. The experimental results show that the embedded processor can be executed like the automatic test equipments, and the test time is reduced and the power consumption is reduced up to 8% at the communication components.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.183-189
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• 2019

Despite its low cost, ARM is widely used in smartphones, digital cameras, home network devices, and wireless technologies because of its low power consumption and reliable performance. The domestic memory semiconductor design technology is in the world's highest level, but that of the processor is far less than that, which results in the technology unbalance between the memory and the processor. When designing a processor, exception and interrupt capabilities are requisite, but this is often omitted in the research stage. However, exception processing and interrupts must be included in order for the processor to function fully. In this paper, we design a 32-bit ARMv4 family of processors with exception handling and interrupts using VHDL and verify with ModelSim. As a result, ARM's exception and interrupts are successfully performed.

• ETRI Journal
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• v.32 no.1
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.236-239
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• 1999

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.