• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.777-779
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• 2014

The LEA(Lightweight Encryption Algorithm) is a 128-bit high-speed/lightweight block cipher algorithm developed by National Security Research Institute(NSRI) in 2012. The LEA encrypts plain text of 128-bit using cipher key of 128/192/256-bit, and produces cipher text of 128-bit, and vice versa. To reduce hardware complexity, we propose an efficient architecture which shares hardware resources for encryption and decryption in round transformation block. Hardware sharing technique for key scheduler was also devised to achieve area-efficient and low-power implementation. The designed LEA cryptographic processor was verified by using FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

• Journal of IKEEE
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• v.21 no.3
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• pp.260-263
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• 2017

Based on several CPU cores, an SoC including ADCs, DC-DC converter and 2M-byte SRAM is proposed in this paper. The CPU core consists of a 12-bit MENSA, a 32-bit Symmetric multi-core processor, as well as 16-bit CDSP. To eliminate the external SDRAM memory, internal 2M-byte SRAM is implemented. Because the SRAM normally occupies huge area, the parasitic components reduce the speed of SoC. In this work, the SRAM blocks are divided into small pieces to reduce the parasitic components. The proposed SoC is developed in a standard 55nm CMOS process and the speed of SoC is 200MHz.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.3
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• pp.201-207
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• 2020

With the expansion in the use of DC power systems and increased need for system maintenance, the development of measurement devices for maintenance requires high stability. Of the different kinds of DC current measurement devices, the single-shot measurement device causes the input signal of the current measuring unit to initially generate a high inrush current. The high inrush current flows into the signal processor of the meter, shortening the life of the internal fuses and causing failure. Therefore, in this study, the I²t value for increasing the durability of the fuse is designed using the available wire diameter. Operating characteristics for 210~400% over-current of the rated current, which is relatively low over-current, are realized by the plating of low melting tin metal. As a result, a method of designing a fuse element for a DC power supply, which improves the safety of the DC current measurement device by blocking the failure caused by the inrush current, is presented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.285-287
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• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.292-297
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• 2005

This paper proposes a simple MPPT control scheme of a Current-Control-Loop Error system Based that can be obtains a lot of advantage to compare with another digital control method, P&O and IncCond algorithm, that is applied mostly a PV system. An existent method is needed an expensive processor such as DSP that calculated to change the measure power of a using current and voltage sensor at the once. Therefore, it is applied a small home power generation system that required many expenses. But, a proposed method is easy to solve the cost reduction and power unbalance problems that it is used by control scheme to limit error of a current control of common sensor. This proposed algorithm had verified through a simulation and an experiment on battery charger using PIC that is the microprocessor of a low price.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.451-462
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• 2016

Photovoltaic energy conversion becomes main focus of many researches due to its promising potential as source for future electricity and has many advantages than the other alternative energy sources like wind, solar, ocean, biomass, geothermal etc. In Photovoltaic power generation multilevel inverters play a vital role in power conversion. The three different topologies, diode-clamped (neutral-point clamped) inverter, capacitor-clamped (flying capacitor) inverter and cascaded h-bridge multilevel inverter are widely used in these multilevel inverters. Among the three topologies, cascaded h-bridge multilevel inverter is more suitable for photovoltaic applications since each pv array can act as a separate dc source for each h-bridge module. This paper presents a single phase Cascaded H-bridge five level inverter for grid-connected photovoltaic application using sinusoidal pulse width modulation technique. This inverter output voltage waveform reduces the harmonics in the generated current and the filtering effort at the input. The control strategy allows the independent control of each dc-link voltages and tracks the maximum power point of PV strings. This topology can inject to the grid sinusoidal input currents with unity power factor and achieves low harmonic distortion. A PID control algorithm is implemented in Arm Processor LPC2148. The validity of the proposed inverter is verified through simulation and is implemented in a single phase 100W prototype. The results of hardware are compared with simulation results. The proposed system offers improved performance over conventional three level inverter in terms of THD.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.367-370
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• 2002

In this paper, we propose a new node architecture LonWorh control Network for home network system environmint using power line communications. Using conventional Lon Work technology is a many disputable points for home network. LonWork network system needs high-cost development equipment. Moreover, conventional Lon Work system can not implement high-grade algorithms and variety application operation. because of the limitation of processing ability in Neuron chip. For that reason, the proposed structure is applicable to low-cost and more complex applications which are impossible in home network using conventional Lonworks structure. The proposed structure is implemented with some hardware and かone software for power line home network. The physical layer and the MAC layer of the LonTalk protocol within ton Work are implemented in hardware, which decreases the development costs communication processor. The upper of link layer of the LonTalk protocol is implemented with software, which decreases the development costs of software and increases the flexibility of tile system and increases the extension of the system. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network in home network. As a result, it is concluded that the proposed architecture provides increasing flexibility and decreasing cost of the system.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1792-1798
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• 2017

Event Data Recorder(Car Black-Box) with WiFi dongle have been released, and the platform of the majority is the Linux platform. This is because the platform development is possible in little investment cost by reducing the source licensing costs by taking advantage of the open source. But utilizing Linux platform has the limitations of boot-up time and consuming processing power due to the limitation of battery capacity, to be cost-competitive to minimize the use of memory. In this paper, the real-time operating system(RTOS) is utilized to optimize these portions. MP4 encoder and Muxer are developed to be about ten seconds boot up and minimized memory. It has the advantages of operating at lower power consumption than the Linux utilizing WiFi dongle. Utilizing a WiFi dongle is to provide a progressive download feature on smart phones to lower product prices. But RTOS has the weakness in WiFi. Porting TCP /IP, Web and DHCP server and combination with the USB OTG Host interface by implementing the protocol stack are developed for WiFi. And also SPI NOR flash memory is utilized for faster boot time and cost reductions, low processing power to be consume. As the results, the developed proved the 10 seconds booting time, 24 frame rate/sec. and 10% lower power consumption.

• The KIPS Transactions:PartA
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• v.16A no.6
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• pp.443-452
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• 2009

Although 32-bit architectures are becoming the norm for modern microprocessors, 16-bit ones are still employed by many low-end processors, for which small size and low power consumption are of high priority. However, 16-bit architectures have a critical disadvantage for embedded processors that they do not provide enough encoding space to add special instructions coined for certain applications. To overcome this, many existing architectures adopt non-orthogonal, irregular instruction sets to accommodate a variety of unusual addressing modes. In general, these non-orthogonal architectures are regarded compiler-unfriendly as they tend to requires extremely sophisticated compiler techniques for optimal code generation. To address this issue, we proposed a compiler-friendly processor with a new addressing mode, called the dynamic implied addressing mode(DIAM). In this paper, we will demonstrate that the DIAM provides more encoding space for our 16-bit processor so that we are able to support more instructions specially customized for our applications. And we will explain the advanced architecture which has improved performance. In our experiment, the proposed architecture shows 11.6% performance increase on average, as compared to the basic architecture.