• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.1
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• pp.33-38
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• 2006

This paper proposes a simple MPPT control scheme of a based Current-Control-Loop system that can be obtains a lot of advantage to compare with another digital control method, P&O(Perturbation and Observation) and IncCond(Incremental Conductance) algorithm, that is applied mostly a PV system. An existent method is needed an expensive processor such as DSP that calculated to change the measure power of a using current and voltage sensor at the once. Therefore, it is applied a small home power generation system that required many expenses. But, a proposed method is easy to solve the cost reduction and power unbalance Problems that it is used by control scheme to limit error of a current control of common sensor. This proposed algorithm had verified through a simulation and an experiment results on battery charger using PIC that is the microprocessor of a low price.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.48 no.6
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• pp.9-16
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• 2011

Due to the development and proliferation of ubiquitous technologies and services, various sensor network applications are being appeared on the stage. The needs for algorithms requiring sensor data fusion and complex signal processing with a high-performance processor such as a digital signal processor are also increased. However, it is difficult to use such processor for the low-power sensor network operating with a battery because of power consumption. This paper proposes a hybrid-type sensor module architecture supporting wakeup/sleep software framework for the wireless sensor node and shows the implemented sensor node platform and performances focused on the energy consumption and wakeup time.

• Journal of the Korea Society of Computer and Information
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• v.15 no.3
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• pp.1-10
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• 2010

As processor platforms are continuously moving toward wireless mobile systems, embedded mobile processors are expected to perform more and more powerful, and therefore the development of an efficient power management algorithm for these battery-operated mobile and handheld systems has become a critical challenge. It is well known that a memory system is a main performance limiter in the processor point of view. Although many DVFS studies have been considered for the efficient utilization of limited battery resources, recent works do not explicitly show the interaction between the processor and the memory. In this research, to properly reflect short/long-term memory access patterns of the embedded workloads in wireless mobile processors, we propose a memory buffer utilization as a new index of DVFS level prediction. The simulation results show that our solution provides 5.86% energy saving compared to the existing DVFS policy in case of memory intensive applications, and it provides 3.60% energy saving on average.

• Journal of Korea Society of Industrial Information Systems
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• v.26 no.5
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• pp.11-19
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• 2021

In this paper, we proposed an asymmetric multi-core processor scheduling scheme which is based on the mileage of each core. We considered a big-LITTLE multi-core processor structure, which consists of low power consuming LITTLE cores with general performance and high power consuming big cores with high performance. If a task needs to be processed, the processor decides a core type (big or LITTLE) to handle the task, and then investigate the core with the shortest mileage among unoccupied cores. Then assigns the task to the core. We developed a mileage-based balancing algorithm for asymmetric multi-core assignment and showed that the proposed scheduling scheme is more cost-effective compared to the traditional scheme from a management perspective. Simulation is also conducted for the purpose of performance evaluation of our proposed algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.56-62
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• 2008

Modern microprocessors must deliver high application performance, while the design process should not subordinate power. In terms of performance and power tradeoff, the instructions window is particularly important. This is because a large instruction window leads to achieve high performance. However, naive scaling conventional instruction window can severely affect the complexity and power consumption. This paper explores an architecture level approach to reduce power dissipation. We propose a low power issue logic with an efficient tag translation. The direct lookup table (DTL) issue logic eliminates the associative wake-up of conventional instruction window. The tag translation scheme deals with data dependencies and resource conflicts by using bit-vector based structure. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces power consumption by 24.45% on average over conventional approach.

• Journal of Power Electronics
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• v.16 no.3
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• pp.1025-1035
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• 2016

Luenberger observer (LO)-based sensorless multi-loop control of a converter requires an iterative trial-and-error design process, considering that many parameters should be determined, and loop gains are indirectly related to the closed-loop characteristics. Robust H∞ control adopts a compact sensorless controller. The algebraic Riccati equation (ARE)-based and linear matrix inequality (LMI)-based H∞ approaches need an exhaustive procedure, particularly for a low-order controller. Therefore, in this study, a novel robust H∞ synthesis approach is proposed to design a low-order sensorless controller for boost converters, which need not solve any ARE or LMI, and to parameterize the controller by an adjustable parameter behaving like a "knob" on the closed-loop characteristics. Simulation results show the straightforward closed-loop characteristics evaluation and better dynamic performance by the proposed H∞ approach, compared with the LO-based sensorless multi-loop control. Practical experiments on a digital processor confirmed the simulation results.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.1
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• pp.53-62
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• 2010

Recently, various industrial embedded systems including vehicles controlled electronically are evolving to distributed multi-micro controller system. Accordingly, there is a need for standard CAN(Controller Area Network) protocol that ensures high stability and reliability of communication and is simple to construct object-oriented system with high control efficiency. CAN communication interface used general-purpose processor doesn't have many limitations in various application development because of fixed hardware architecture. This paper design and implement a CAN communication interface system based on FPGA. It is verified function and performance of system through monitoring communication with existing AT90CAN128 controller. Implemented CAN communication interface can be reused in development of application systems based on FPGA. And it provides low-cost, small-size and low-power design advantages.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.597-598
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• 2008

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.209-212
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• 2002

The realization for code domain analyzing system on WCDMA is presented. This system is realized with the RF, FPGA and DSP processor. The FPGA firgures out the scambling code, and DSP produces the power of code domain using OVSF. The experiment results allow the code domain power accuracy to keep $\pm$1dB low. This system leads to split the text, sound and image signal.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1493-1496
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• 2016

This paper proposes a system for reducing the standby power consumption in using the consumer electronic devices such as a television, a home theater, a set-top box, or a DVD player. The system is consisted of a flyback converter, monitoring circuits, a relay and a micro-processor. The proposed system can reduce the standby power consumption by disconnecting the AC input and the consumer devices can be turned on with a remote control. The proposed standby power system consumes the low power to receive the infrared signal from the remote controller. Furthermore, a electronic double layer capacitor is used to store the energy with high efficiency. The proposed power system can operate the 플라이백 converter to charge the electronic double layer capacitor and connect the AC input to the consumer electronic devices. The proposed power circuit can reduce the standby power consumption in AV devices without increasing the cost. The prototype is implemented to verify the system with the commercialized products.