• Title/Summary/Keyword: Low-power processor

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A Study on the Data Aquisition System for Power Quality Analysis of Load Equipment (부하설비의 전력품질 분석을 위한 데이터 획득시스템에 관한 연구)

  • Yu, Jae-Geun;Lee, Sang-Ik;Choe, Gyu-Ha
    • Proceedings of the KIPE Conference
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    • 2007.07a
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    • pp.92-94
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    • 2007
  • In order to analyze voltage, current, electrical power, harmonics and so on of electrical load equipments, electrical power analysis by real measurement rather than mathematical modeling is necessary, and plan of countermeasure for efficient management, energy frugality and accident prevention of electrical equipments using it is possible. Especially, electrical power analysis by real measurement is indispensable in order to consider countermove of harmonic occurred by nonlinear load. So, in this paper, we developed DSP(Digital Signal Processor) based low price date aquisition system, and verified it's ability by performing measurement and analysis of electrical power and harmonic in the real power system.

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Study on High Efficiency Boosting-up Circuit for Renewable Energy Application (신재생에너지용 연계형 인버터의 고효율 승압에 관한 연구)

  • Jung, Tae-Uk;Kim, Ju-Yong;Choi, Se-Kwon;Cho, Jun-Seok;Kho, Hee-Seok
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2009.05a
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    • pp.336-339
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    • 2009
  • In this paper, such as battery power or solar energy and fuel cells generated from Renewable energy sources, high voltage to low voltage DC-DC Converter for converting the design of the study. System consists of low voltage ($24{\sim}28$ [VDC]) and Boosts the voltage (270 [VDC]) for a 3 [kW] DC-DC converter and control circuit is configured as, Power switch the ST Tomson's Automotive low voltage high current MOSFET switches STE250NS10S (temperature 250A) was applied to the two parallel. Also, Controller's processor used ATMEGA128, and Gate Drive applies and composed Photo Coupler TLP250. development. Input voltage (24V) and output voltage (270V) for Conversion in the H-bridge converter topology of the circuit output side power and voltage to control the implementation of the Phase shift angle control applied. And, 3kW of power to pass appropriate specification of the secondary side as interpreted by the high frequency transformer, and the experimental production and analysis of the experiment

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The Improvement Techniques of Characteristics using DSP Chip in Switching Power Converter System (DSP칩을 이용한 스위칭 전력변환 시스템의 특성 개선 기법)

  • Kang Min-Su;Kim Sang-Ug;Im Dong-Gi;Kang Ho-Hyun;Jeon Hee-Jong
    • Proceedings of the KIPE Conference
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    • 2004.07b
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    • pp.670-672
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    • 2004
  • In this paper, single phase boost converter with low current harmonic components and high power factor are proposed. A single-phase half-bridge rectifier based on a neutral point switch clamped scheme is proposed to draw a nearly unity power factor and regulate the DC link voltage. Three power switches are employed in the proposed rectifier. This rectifier is controlled to generate a bipolar or unipolar PWM voltage waveform on the AC side. The proposed converter is implemented by a digital signal processor.

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A Development Of Utility Vehicle Controller With Photovoltaic Power System (태양광 발전 겸용 유틸리티 차량용 컨트롤러의 개발)

  • 김태엽;안호균
    • The Transactions of the Korean Institute of Power Electronics
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    • v.5 no.5
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    • pp.467-474
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    • 2000
  • This paper describes the development of 7he utility vehicle controller using combination system of battery and photovoltaic power for increasing operation time. In order to keep interchangeability, low cost and high performance, a separately excited DC Motor is controlled without velocity and current measurements by $\mu$-processor. For the parallel operation between the solar cell and battery, dc-dc converter is used, which is applied to the maximum power Point tracking(MPPT) and current control algorithm. By the simulation and experimental results of trial product, the vapidity of the proposed system is verified.

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Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

  • Deivakani, M.;Shanthi, D.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.736-744
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    • 2016
  • Network on chip (NoC) is an emerging technology in the field of multi core interconnection architecture. The routers plays an essential components of Network on chip and responsible for packet delivery by selecting shortest path between source and destination. State-of-the-art NoC designs used routing table to find the shortest path and supports four ports for packet transfer, which consume high power consumption and degrades the system performance. In this paper, the multi port multi core router architecture is proposed to reduce the power consumption and increasing the throughput of the system. The shared buffer is employed between the multi ports of the router architecture. The performance of the proposed router is analyzed in terms of power and current consumption with conventional methods. The proposed system uses Modelsim software for simulation purposes and Xilinx Project Navigator for synthesis purposes. The proposed architecture consumes 31 mW on CPLD XC2C64A processor.

MTCMOS ASIC Design Methodology for High Performance Low Power Mobile Computing Applications (고성능 저전력 모바일 컴퓨팅 제품을 위한 MTCMOS ASIC 설계 방식)

  • Kim Kyosun;Won Hyo-Sig
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.31-40
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    • 2005
  • The Multi-Threshold CMOS (MTCMOS) technology provides a solution to the high performance and low power design requirements of mobile computing applications. In this paper, we (i) motivate the post-mask-tooling performance enhancement technique combined with the MTCMOS leakage current suppression technology, and (ii) develop a practical MTCMOS ASIC design methodology which fine-tunes and integrates best-in-class techniques and commercially available tools to fix the new design issues related to the MTCMOS technology. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um Process. The fabricated PDA processor operates at 333MHz which has been improved about $23\%$ at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

Implementation of a 32-Bit RISC Core for Multimedia Portable Terminals (멀티미디어 휴대 단말기용 32 비트 RISC 코어 구현)

  • 정갑천;기용철;박성모
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.226-229
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    • 2000
  • In this paper, we describe implementation of 32-Bit RISC Core for portable communication/information equipment, such as cellular telephones and personal digital assistants, notebook, etc. The RISC core implements the ARM$\^$R/V4 instruction set on the basis of low power techniques in architecture level and logic level. It operates with 5-stage pipeline, and has harvard architecture to increase execution speed. The processor is modeled and simulated in RTL level using VHDL. Behavioral Cache and MMU are added to the VHDL model for instruction level verification of the processor. The core is implemented using Mentor P'||'&'||'R tools with IDEC C-631 Cell library of 0.6$\mu\textrm{m}$ CMOS 1-poly 3-metal CMOS technology.

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High-performance Digital Hearing Aid Processor Chip with Nonlinear Multiband Loudness Correction (비선형 다중채널 Loudness 교정을 위한 고성능 보청기 칩)

  • Park, Young-Cheol;Kim, Dong-Wook;Kim, Won-Ky;Park, Sang-Il
    • Proceedings of the KOSOMBE Conference
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    • v.1997 no.05
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    • pp.342-344
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    • 1997
  • Owing to technical advances in very large-scale integrated circuits (VLSI), high-speed digital signal processing (DSP) chips become fast enough to allow for real-time implementation of hearing aid algorithms in units small enough to be wearable. In this paper, we present a digital hearing aid processor (DHAP) chip built around a general-purpose 16-bit DSP core. The designed DHAP performs a nonlinear loudness correction of 8 octave frequency bands based on audiometric measurements. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the has a low power feature and $5.410\times5.720mm^2$ dimensions that fit for wearable devices.

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Miniaturization of Signal Processor of Airborne Tracking Radar (항공용 추적 레이더의 신호처리기 소형화 설계)

  • Kim, Doh-Hyun;Lee, Young-Sung;Lee, Hyung-Woo;Kim, Soo-Hong;Kim, Young-Chae
    • Proceedings of the KIEE Conference
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    • 2002.11c
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    • pp.114-117
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    • 2002
  • The airborne tracking radar is located in front of aircraft or missile and measures and tracks a target motion. The signal processor receives target signals from a receiver using A/D converters, and calculates the target motion, and transfers the data to the aircraft or missile control unit. Since the signal processing system is required to be lightweight and small size as well as high performance to calculate and analyze the received signal, we use high speed DSPs and SMD type components having low power consumption. In this paper, we describe the design concept of signal processing system of the airborne tracking radar.

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Design and implementation of thermoelectric dehumidifier using pottier module (Pottier소자를 이용한 열전 제습기 설계 및 구현)

  • 장재철;양규식
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.3 no.3
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    • pp.671-679
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    • 1999
  • In this paper, humidity measurement is accomplished using humidity sensor, dehumidify is implemented using general-purpose $\mu$-processorPIC16C54 and thermoelectric module for control measured humidity and input target humidity value proportionally Pottier module product is variety kind of size and characteristic, very important drawing factor is selection necessary heat sink, which is maintain proper thermal resistance from variety kind of module also. From electronic dehumidifier is manufacture by using thermoelectric module, no sound, no vibration, low power consumption of partial space efficient dehumidify proves the validity of this system.

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