• 전력전자학회논문지
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• 제17권5호
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• pp.416-422
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• 2012

This paper proposes a low power-loss current measurement using a resistor and bypass switch. Conventional current sensing method using a resistor has a disadvantage of power loss which degrades the efficiency of the entire systems. On the other hand, proposed measurement technique operating with bypass-switch connected in parallel with sensing resistor can reduce power loss significantly the current sensor. The propose measurement works for discrete-time sampling of current sensing. Even while the analog-digital conversion does not occur at the controller, the sensing voltage across the sensor still causes ohmic conduction loss without information delivery. Hence, the bypass switch bypasses the sensing current with a small amount of power loss. In this paper, a 90[W] prototype hardware has been implemented for photovoltaic MPPT experimental verification of the proposed low power-loss current measurement technique. From the results, it can be seen that PV power observation is successfully done with the proposed method.

• 센서학회지
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• 제26권1호
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• pp.60-65
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• 2017

This paper describes the low noise and low power IC using the opamp sharing technique for the capacitive micro-sensor sensing platform. The proposed IC reduces noise using correlated double sampling (CDS) and reduces power consumption using the opamp sharing technique. The IC is designed to be fully programmable, and can be digitally controlled by serial peripheral interface (SPI). The power consumption and the integrated input referred noise are 1.02 mW from a 3.3 V supply voltage and $0.164aF_{RMS}$ with a bandwidth of 400 Hz. The capacitive sensitivity, the input-output linearity and the figure of merits (FoM) are 2.5 mV/fF, 2.46 %FSO, and 8.4, respectively.

• 전자공학회논문지C
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• 제34C권12호
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• pp.20-27
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• 1997

In this paper, a multiplying digital-to-analog converter (MDAC) circuit for low-power high-resolution CMOS algorithmic A/D converters (ADC's) is proposed. The proposed MDAC is designed to operte properly at a supply at a supply voltge between 3 V and 5 V and employs an analog0domain power reduction technique based on a bias switching circuit so that the total power consumption can be optimized. As metal-to-metal capacitors are implemented as frequency compensation capacitors, opamps' performance can be varied by imperfect process control. The MDAC minimizes the effects by the circuit performance variations with on-chip tuning circuits. The proposed low-power MDAC is implementd as a sub-block of a 10-bit 200kHz algorithmic ADC using a 0.6 um single-poly double-metal n-well CMOS technology. With the power-reduction technique enabled, the power consumption of the experimental ADC is reduced from 11mW to 7mW at a 3.3V supply voltage and the power reduction ratio of 36% is achieved.

• Journal of Power Electronics
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• 제5권3호
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• pp.190-197
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• 2005

This paper presents a technique to reduce the low frequency ripple voltage of the dc output in a BIFRED converter with a small-sized energy storage capacitor. The proposed pulse width control method can be effectively used to suppress the low frequency ripple appeared in the dc output and still maintains generally good performance such as low THD of input line current and a high power factor. Using the small-sized energy storage capacitor, it has better merits of low cost and smaller size than a conventional BIFRED converter. The proposed technique is illustrated its validity and effectiveness through simulations.

• Journal of Power Electronics
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• 제19권3호
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• pp.645-654
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• 2019

In this paper, a new high step up DC/DC converter with a modified super-lift technique is presented. The coupled inductor technique is combined with the super-lift technique to provide a tenfold or more voltage gain with a proper duty cycle and a low turn ratio. Due to a high conversion ratio, the voltage stress on the semiconductor devices is reduced. As a result, low voltage ultra-fast recovery diodes and low on resistance MOSFET can be used, which improves the reverse recovery problems and conduction losses. This converter employs a passive clamp circuit to recycle the energy stored in the leakage inductance. The proposed convertor features a high conversion ratio with a low turn ratio, low voltage stress, low reverse recovery losses, omission of the inrush currents of the switch capacitor loops, high efficiency, small volume and reduced cost. This converter is suitable for renewable energy applications. The operational principle and a steady-state analysis of the proposed converter are presented in details. A 200W, 30V input, 380V output laboratory prototype circuit is implemented to confirm the theoretical analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 D
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• pp.3121-3123
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• 2000

Power line communications is a topic which has been studied for many years, However. the technology has not been widely adopted for data networking in homes and small businesses due to low speed. low functionality. and other barriers. Recently. with a proper technology. it is shown that the power line infrastructure can also be served as a high-speed communications medium. This paper describes a transmission scheme for power lines that is based on orthogonal frequency division multiplex(OFDM) technique. This technique can be used for high-speed data communication over the power line. This paper also presents an adaptive tracking algorithm which allocate bits and power adaptively according to the channel characteristics. The performance of the proposed scheme has been demonstrated by some simulations with taking modeled channel conditions into account.

• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• ETRI Journal
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• 제33권1호
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• pp.140-143
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• 2011

Recent test data compression techniques raise concerns regarding power dissipation and compression efficiency. This letter proposes a new test data compression scheme, twin symbol encoding, that supports block division skills that can reduce hardware overhead. Our experimental results show that the proposed technique achieves both a high compression ratio and low-power dissipation. Therefore, the proposed scheme is an attractive solution for efficient test data compression.

• 한국정보통신학회논문지
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• 제18권8호
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• pp.1877-1884
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• 2014

원격 무선 네트워크 환경에서의 무인 센서 신호처리기의 임무 수행을 위해서는 한정된 전력 자원으로 인해 무인 원격 센서 무선운용 상황에 적합한 신뢰성 있는 저전력 매체 접속 제어 기법이 요구된다. 저전력 무선 네트워크에서 효과적인 신호 전송을 위해서는 CSMA/CA, X-MAC을 일반적으로 고려한다. 본 논문에서는 고정 노드로 구성되는 무선 네트워크에서 노드 제어를 위한 이동 노드의 망 참여/탈퇴가 유동적인 망 형태에서의 신속한 데이터 전달 및 소모 전력 최소화 달성이 가능한 저전력 성능이 향상된 LP-MAC 동작 기법을 제안한다. 고정노드는 망 자율구성을 수행하여 망에 수시로 참여/탈퇴하는 이동 노드로의 빠른 정보 전달을 위해 비동기 방식으로 동작한다. 이동 노드가 망에서 탈퇴할 경우, 망 전체 운용모드가 소모 전력의 최소화를 위한 동기모드로 천이됨으로써 최소 전력 운용이 가능한 매체접속 제어 기법이다.

• 전기학회논문지P
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• 제66권4호
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• pp.247-251
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• 2017

This paper proposes a low power transmission technique for single-carrier modulation with frequency domain equalization. As time domain signals and frequency domain signals have unique corresponding functions, inserting zeros after each symbol causes a repetition in other domain, so maximal ratio combining technique using repetitive transmission can be applied in the frequency domain. In this paper, we configure transmit signals to insert zeros after each symbols for single-carrier modulation with frequency domain equalization and maximal ratio receive combining block in the receiver structures, propose a structure for transmitter and receiver and show that its performance is better than the traditional algorithm by simulations.