• Smart Structures and Systems
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• 제10권3호
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• pp.271-298
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• 2012

Researchers have made significant progress in recent years towards realizing effective structural health monitoring (SHM) utilizing wireless smart sensor networks (WSSNs). These efforts have focused on improving the performance and robustness of such networks to achieve high quality data acquisition and distributed, in-network processing. One of the primary challenges still facing the use of smart sensors for long-term monitoring deployments is their limited power resources. Periodically accessing the sensor nodes to change batteries is not feasible or economical in many deployment cases. While energy harvesting techniques show promise for prolonging unattended network life, low power design and operation are still critically important. This research presents the WiSeMote: a new, fully integrated ultra-low power wireless smart sensor node and a flexible base station, both designed for long-term SHM deployments. The power consumption of the sensor nodes and base station has been minimized through careful hardware selection and the implementation of power-aware network software, without sacrificing flexibility and functionality.

• 한국컴퓨터정보학회논문지
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• 제20권7호
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• pp.57-64
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• 2015

In this paper, we propose a design of microwave motion detector using X-band doppler radar sensor to minimize the power consumption. To minimize the power consumption and implement battery operated system, pulse input with 2 KHz, 4% duty cycle is exerted on the doppler radar sensor. In order to simplify the process of working with ATmega2560 microcontroller unit, Arduino compatible board is designed and implemented. Arduino is open source hardware and many library software is published as open source tools. Smartphone app is also proposed and designed as a real-time user interface of the motion detector. The SQLite database on the Android mobile operating system is used for recording raw data of motion detection for post-processing job, such as fast Fourier transform (FFT). Bluetooth interface module is implemented on the motion detection board as a wireless communication interface to the smartphone. The speed of human movement is identified by post-processing FFT.

• ETRI Journal
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• 제39권3호
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 추계종합학술대회 논문 초록집
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• pp.276-276
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• 2004

• Journal of Electrical Engineering and Technology
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• 제11권6호
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• pp.1656-1663
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• 2016

A capacitive wireless power transfer (C-WPT) system uses an electric field to transmit power through a physical isolation barrier which forms a pair of ac link capacitors between the metal plates. However, the physical dimension and low dielectric constant of the interface medium severely limit the effective link capacitance to a level comparable to the main switch output capacitance of the transmitting circuit, which thus narrows the soft-switching range in the light load condition. Moreover, by fundamental limit analysis, it can be proved that such a low link capacitance increases operating frequency and capacitor voltage stress in the full load condition. In order to handle these problems, this paper investigates optimal design of double matching transformer networks for C-WPT. Using mathematical analysis with fundamental harmonic approximation, a design guideline is presented to avoid unnecessarily high frequency operation, to suppress the voltage stress on the link capacitors, and to achieve wide ZVS range even with low link capacitance. Simulation and hardware implementation are performed on a 5-W prototype system equipped with a 256-pF link capacitance and a 200-pF switch output capacitance. Results show that the proposed scheme ensures zero-voltage-switching from full load to 10% load, and the switching frequency and the link capacitor voltage stress are kept below 250 kHz and 452 V, respectively, in the full load condition.

• 한국콘텐츠학회논문지
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• 제7권2호
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• pp.92-99
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• 2007

본 논문은 기존의 블록 암호 프로세서를 128-bit 구조에서 32-bit구조로 소형화시킨 저 전력 구조를 제안하였다. 본 논문의 목적은 암호 이론 연구가 아닌 실용화 연구로서 실용화 결과를 보이는 것이다. 제안된 구조는 하드웨어 크기를 줄이기 위해 데이터 패스와 확산 함수가 수정되었다. 저전력 암호회로의 예로서 ARIA 알고리즘을 고쳐서 4개의 S-box가 사용되었다. 제안된 32-bit ARIA는 13,893 게이트로 구성되어있으며 기존 128-bit 구조보다 68.25% 더 작다. 설계된 회로는 매그너칩스의 0.35um CMOS 공정을 기반으로 표준 셀 라이브러리를 이용하여 합성되었다. 트랜지스터 레벨에서 전력 시뮬레이션 결과 이 회로의 전력 소모는71MHz에서 기존의 128-bit ARIA구조의 9.7%인 61.46mW으로 나타났다. 이 저전력 블록 암호 회로는 전원이 없는 무선 센서 네트워크 또는 RFID 정보보호에 핵심요소가 될 것이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.593-596
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• 2004

This paper presents a low power design of the embedded 3D graphics rendering processor with the double span processing stage. The increase of hardware complexity by using the double span processing stage is ignorable. And the performance is equal to the rendering processor with the single span processing stage. It reduces the power consumption by using different clock frequencies.

• 대한임베디드공학회논문지
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• 제3권1호
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• pp.34-41
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• 2008

There are many researches to build up ubiquitous environment by the Ubiquitous Sensor Network(USN). These applications, such as home network, health care, natural environment and agricultural areas, are implemented by an embedded system. Their fields are gradually spreading. However the power consumption in its implementation plays an important role on the surrounding environment of the wireless network. In this paper, we design low power processor based sensor node platform for agricultural applications. We also compare its some performance with existing products.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.372-376
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• 2001

Due to several advantages of Pulse Width Modulation(PWM) Converter, such as unity power factor operation, elimination of low-order harmonics and regeneration of motor braking energy to source, the application range of PWM Converter has been rapidly extended in industrial application. Nowadays, vector control algorithm and space vector PWM(SVPWM) method are applied to improve the performances of PWM Converter, but vector control algorithm and SVPWM require to use Microprocessor and other digital devices in hardware, causing costly and somewhat large dimension system. In every practical application of energy conversion equipments, the design and implementation should be carried out considering cost and performance. High performance and low cost is the best choice for energy conversion equipments. So, this paper presents the practical design method and implementation results of 3-phase PWM Converter with analog hysteresis current controller, and verifies the performances of unit power factor operation and energy regeneration operation via experimental results.

• ETRI Journal
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• 제32권4호
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• pp.540-547
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• 2010

One of the critical issues in on-chip serial communications is increased power consumption. In general, serial communications tend to dissipate more energy than parallel communications due to bit multiplexing. This paper proposes a low-power bus serialization method. This encodes bus signals prior to serialization so that they are converted into signals that do not greatly increase in transition frequency when serialized. It significantly reduces the frequency by making the best use of word-to-word and bit-by-bit correlations presented in original parallel signals. The method is applied to the revision of an MPEG-4 processor, and the simulation results show that the proposed method surpasses the existing one. In addition, it is cost-effective when implemented as a hardware circuit since its algorithm is very simple.