• 센서학회지
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.37-38
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• 2013

This paper presents an intuitive and powerful way to study and design motor drive control. The control of induction motors, as most widely used machines, is discussed. Thanks to ultra low latency and high fidelity Hardware-in-the-Loop systems, different aspects of up-to-date drive regulation are examined. A power stage, comprised of a grid voltage source, a rectifier, a VSC inverter and an induction motor, is emulated on the HIL platform in real time. A digital signal controller is plugged into the interface board and connected to the HIL emulation platform, without any hardware modifications. For motor control and power electronics applications, a dedicated Texas Instruments TMS320F2808 DSP is chosen. The same controller can drive an emulation platform and a real device with no modifications. Current and speed control loop test results are presented and discussed.

• ETRI Journal
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• 제45권4호
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• pp.570-580
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• 2023

Sensor nodes are the most significant part of a wireless sensor network that offers a powerful combination of sensing, processing, and communication. One major challenge while designing a sensor node is power consumption, as sensor nodes are generally battery-operated. In this study, we proposed the design of a low-power, long range-based wireless sensor node with flexibility, a compact size, and energy efficiency. Furthermore, we improved power performance by adopting an efficient hardware design and proper component selection. The Nano Power Timer Integrated Circuit is used for power management, as it consumes nanoamps of current, resulting in improved battery life. The proposed design achieves an off-time current of 38.17309 nA, which is tiny compared with the design discussed in the existing literature. Battery life is estimated for spreading factors (SFs), ranging from SF7 to SF12. The achieved battery life is 2.54 years for SF12 and 3.94 years for SF7. We present the analysis of current consumption and battery life. Sensor data, received signal strength indicator, and signal-to-noise ratio are visualized using the ThingSpeak network.

• 전기학회논문지
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• 제65권1호
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• pp.88-96
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• 2016

In this paper, the GaN FET based phase-shift full-bridge dc-dc converter design is implemented. Switch characteristics of GaN FET were analyzed in detail by comparing state-of-the-art Si MOSFET. Owing to the low conduction resistance and parasitic capacitance, it is expected to GaN FET based power conversion system has improved performance. However, GaN FET is vulnerable to electric interference due to the relatively low threshold voltage and fast switching transient. Therefore, it is necessary to consider PCB layout to design GaN FET based power system because PCB layout is the main reason of stray inductance. To reduce the electric noise, gate voltage of GaN FET is analyzed according to operation mode of phase-shift full-bridge dc-dc converter. Two 600W phase-shifted full-bridge dc-dc converter are designed based on the result to evaluate effects of stray inductance.

• ETRI Journal
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• 제25권5호
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• 한국통신학회논문지
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• 제31권3A호
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• pp.360-367
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• 2006

본 논문에서는 RFID 표준 중의 하나인 EPC 글로벌 제너레이션 2 클래스 1(EPC global generation 2 class 1) 태그의 설계에 대하여 논하였다. RFID 표준에 관한 연구나 충돌 방지(anti-collision) 알고리즘에 관한 연구는 많이 진행이 되었지만 태그디지털 코덱 아키텍처 하드웨어의 구체적인 설계에 관한 논문은 아직 없는 실정이기 때문에 본 논문에서 연구하게 되었다. 본 논문의 목적은 RFID 태그 블록의 구성 및 기능설계에 관한 연구를 함으로써 대략적인 전력소모, 하드웨어 크기 등에 대한 방향을 제시하고있다. 스탠더드 셀 라이브러리 합성방식을 사용하여 합성한 결과 설계된 디지털 코덱의 크기는 111640.328125개(인버터 개수)였고 소모 전력은 동적 소모 전력을 기준으로 10.3575uW로 추정되었다. 풀커스텀(full-custom)방식을 사용할 경우, 더욱 개선된 효과를 발휘할 것으로 보인다.

• 한국군사과학기술학회지
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• 제15권6호
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• pp.761-769
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• 2012

In this paper, we propose a low-power design strategy to minimize energy-consumption for surveillance and reconnaissance sensor networks. The sensor network consists of many different nodes with various operations such as target detection, packet relay, video monitoring, changing protocols, and etc. Each sensor node consists of sensing, computing, communication, and power components. These components are integrated on a single or multiple boards. Therefore, the power consumption of each component can be different on various operation types. First, we identified the list of components and measured power consumption for them from the first prototype nodes. Next, we focus on which components are the main sources of energy consumption. We propose many energy-efficient approaches to reduce energy consumption for each operation type.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1085-1088
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• 1998

In this paper, we propose a hardware reduced multiplier for DSP applications. In many DSP application, all of multiplier products were not used, but only upper bits of rpoduct were used. Kidambi proposed truncated unsigned multiplier for this idea. In this paper, we abopt this scheme to Booth multiplier which can be used for real DSP systems. Also, zero input guarantees zero output that was not provided in the previous work.

• 한국전자통신학회논문지
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• 제13권5호
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• pp.1037-1042
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• 2018

최근 인간의 뇌를 모방하여 정보를 학습하고 처리하는 뉴로모픽 기술에 대한 연구는 꾸준히 진행되고 있다. 뉴로모픽 시스템의 하드웨어 구현은 다수의 간단한 연산절차와 고도의 병렬처리 구조로 구성이 가능하여, 처리속도, 전력소비, 저 복잡도 구현 측면에서 상당한 이점을 가진다. 또한 저 전력, 소형 임베디드 시스템에 적용 가능한 뉴로모픽 기술에 대한 연구가 급증하고 있으며, 정확도 손실 없이 저 복잡도 구현을 위해서는 입력데이터의 차원축소 기술이 필수적이다. 본 논문은 멀티모달 센서 데이터를 처리하기 위해 멀티모달 센서 시스템, 다수의 뉴론 엔진, 뉴론 엔진 컨트롤러 등으로 구성된 경량 인공지능 엔진과 특징추출기를 설계 하였으며, 이를 위한 병렬 뉴론 엔진 구조를 제안하였다. 설계한 인공지능 엔진, 특징 추출기, Micro Controller Unit(MCU)를 연동하여 제안한 경량 인공지능 엔진의 성능 검증을 진행하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.875-878
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• 1998

In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.