• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1868-1872
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• 2010

The LED illuminator has merits that it has low power consumption, long life and emits low Co2 gas. As it has many merits in comparison with existing illuminator it is a realistic alternative. but its possession in illuminator market shows slow increasement unexpectedly. Because its price is very high only low power consumption can not keep pace with economical efficiency. In this paper I analyzed economical efficiency about LED illuminator when it is applied at subway station.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.125-131
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• 2018

STT-RAM is attracting as a next generation Non-volatile memory for replacing cache memory with low leakage energy, high integration and memory access performance similar to SRAM. However, there is problem of write operations as the other Non_volatile memory. Hybrid cache memory using SRAM and STT-RAM is attracting attention as a cache memory structure with lowe power consumption. Despite this, reducing the leakage energy consumption by the STT-RAM is still lacking access to the Dynamic energy. In this paper, we proposed as energy management method such as a way-selection approach for hybrid L2 cache fo SRAM and STT-RAM and memory selection method of write/read operation. According to the simulation results, the proposed hybrid cache memory reduced the average energy consumption by 40% on SPEC CPU 2006, compared with SRAM cache memory.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.58-61
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• 2007

We present simulations and results to demonstrate the viability of stainless steel foil as a substrate for low power consumption, flexible AMOLED displays. Using organic planarization layers, we achieve very smooth surface properties, resulting in excellent TFT performance, that can be repetitively flexed without significantly affecting device performance. The use of phosphorescent OLEDs enables the design of low power consumption 40" AMOLED displays.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.463-465
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• 2008

This article describes a design and implementation of low power consumption wireless sensor network platform for intelligent motorway monitoring. There are many dangerous situations on motorway, foggy weathers, rapidly changes of temperature, etc. We designed a system for monitoring motorway environment for report dangerous situation. We introduce this system and its lowpower consumption characteristics which important to battery based system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.1
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• pp.30-40
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• 2010

The hard disk is one of the most frequently used storage in IPTV sep-top box. It has large storage capacity and provides fast I/O speed compared to its price whereas it causes high power consumption due to mechanical characteristics of spindle motor. In order to play streaming data in the set-top box, spindle motor of hard disk keeps active mode and it causes high power consumption. In this paper, We propose an offset-buffering and multi-mode spin-down method to reduce power consumption for streaming data playback. The offset-buffering inspects the user's viewing pattern and performs buffering based on the analysis of viewing pattern. So, it can maintain the status of spindle motor as idle mode for long time. Besides, it can reduce power consumption by spinning down according to offset-buffer size. The experimental result shows that proposed offset-buffering and multi mode spin-down method is about 28.3% and 12.5% lower than the full-Buffering method in terms of the power consumption and spin-down frequency, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.95-104
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• 2004

This paper propose a motion estimator architecture to reduce the power consumption of the most-power-consuming motion estimation method when designing multimedia SoC with deep submicron technologies below 0.13${\mu}{\textrm}{m}$. The proposed architecture considers both dynamic and static power consumption so that it is suitable for large leakage process technologies, while conventional architectures consider only dynamic power consumption. Consequently, it is suitable for mobile information terminals such as mobile videophone where efficient power management is essential. It exploits full search method for simple hardware implementation. It also exploits early break-off method to reduce dynamic power consumption. To reduce static power consumption, megablock shutdown method considering power line noise is also employed. To evaluate the proposed architecture when applied multimedia SoC, system-level control flow and low-power control algorithm are developed and the power consumption was calculated based on thor From the simulation results, power consumption was reduced to about 60%. Considering the line width reduction and increased leakage current due to heat dissipation in chip core, the proposed architecture shows steady power reduction while it goes worse in conventional architectures.

• Journal of Drive and Control
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• v.17 no.2
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• pp.38-44
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• 2020

Various efforts have been initiated to reduce the energy consumption of the compressor as it is one of the approaches to saving a large portion of the fixed cost of the production site. Various results of reducing the energy consumption of the compressor have been reported, but to reduce the energy consumption of the compressors fundamentally, regular management of the compressor should ensure optimum operation. This requires periodic on-site visits by experts, but is often overlooked as a cost issue, resulting in the use of the compressor in low-efficiency conditions. Thus, it is necessary to develop a low-cost evaluation technology for compressor condition monitoring and efficiency analysis to ensure that the compressor is always driven at the optimum efficiency without imposing undue burden on the compressor user. In this study, a sensor was installed at the inlet, outlet, and power supply of the compressor, and a method for evaluating the energy consumption of the compressor using the minimum sensor was derived. The experimental results are presented to show the validity of the proposed method. It was confirmed that the energy consumption of the compressor can be easily as well as efficiently evaluated by using the method developed in this study.

• Journal of IKEEE
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• v.12 no.4
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• pp.211-216
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• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Transactions on Semiconductor Engineering
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• v.1 no.1
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• pp.14-22
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• 2023

This paper presents a low-power flip-flop(FF) circuit that minimizes the transition of internal nodes by using a dual change-sensing method. The proposed dual change-sensing FF(DCSFF) shows the lowest dynamic power consumption among conventional FFs, when there is no input data transition. From the measured results with 65nm CMOS process, the power consumption has been reduced by 98% and 32%, when the data activity is 0% and 100%, respectively, compared to conventional transmission gate FF(TGFF). Further, compared to change-sensing FF(CSFF), the power consumption of proposed DCSFF is smaller by 30%.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.3
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• pp.115-121
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• 2015

A device which could cut off the consumption of standby power by electric or electronic devices at homes and offices while waiting for a command to carry out the main functions from the inside or the outside was developed at a low price. Efforts to save standby power have been made on a global scale as well as by advanced countries. The consumption of standby power in South Korea is also increasing gradually due to increasing trend in the number of electronic and electric devices per household, becoming a major factor for waste of electric energy. The previous standby power cutoff devices themselves have high electric energy consumption and complicated structures, making the purpose less meaningful. Therefore, a low-priced standby power cutoff device is suggested in this study, which compensates such problems and cuts off the consumption of standby power completely. The circuit of the suggested standby power cutoff device was designed and implemented by applying it to an earth leakage breaker and an (electrical) outlet. Experimental results show its superiority.