• The Transactions of the Korean Institute of Electrical Engineers P
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• v.64 no.1
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• pp.29-34
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• 2015

DC bus electrolytic capacitors are used in variety of equipments as smoothing element of the power converters because it has high capacitance for its size and low price. It is responsible for frequent breakdowns of many static converters and inverter drive systems. Therefore it is important to diagnosis monitoring the condition of an electrolytic capacitor in real-time to predict the failure of power converter. In this paper, the on-line remote diagnosis monitoring system for DC BUS electrolytic capacitors of power converter using low-cost type Zigbee communication modules is developed. To estimate the health status of the capacitor, the equivalent series resistor(ESR) of the component has to be determined. The capacitor ESR is estimated by using RMS computation using AC coupling method of DC link ripple voltage/current. The Zigbee communication-based experimental results show that the proposed remote DC capacitor diagnosis monitoring system can be applied to DC/DC converter and UPS successfully.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.7
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• pp.71-79
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• 2004

Packet-type data transmission is characterized by the continuous transmission of massive data with relatively constant rate. In such transmission, the dynamic power consumed on buses is influenced by the sequence of transmitted data. A new coding scheme called Sequence-Switch Coding (SSC) is proposed in this paper. SSC reduces the number of bus transitions in the transmission of packet-type data by changing the sending order of the data. Some simple algorithms are presented, In. The simulation results show that SSC outperforms the well-known Bus-Invert Coding with these algorithms. SSC is not a specific algerian but a method to reduce the number of bus-transitions. There could be lots of algorithms for realizing SSC. The variety of SSC algorithms provides circuit designers a wide range of trade-off between performance and circuit complexity.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.55-57
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• 2007

A Power control and Distribution Unit (PCDU) plays roles of protection of battery against overcharge by active control of solar array generated power, distribution of unregulated electrical power via controlled outlets to bus and instrument units, distribution of regulated electrical power to selected bus and instrument units, and provision of status monitoring and telecommand interface allowing the system and ground operate the power system, evaluate its performance and initiate appropriate countermeasures in case of abnormal conditions. In this work, we perform the preliminary design of a PCDU for the small Low Earth Orbit (LEO) Satellite applications. The main constitutes of the PCDU are the battery interface module, solar array regulators with maximum power point tracking (MPPT) technology, heater power distribution modules, internal converter modules for regulated bus voltage generation, power distribution modules of unregulated and regulated primary bus, and instrument power distribution modules.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.3
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• pp.165-172
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• 2003

This paper presents an operation scheme to enhance the power system security by applying FACTS on Power systems. Three main generic types of FACTS devices are suggested an illustrated. Flow congestions over lines have been solved by controlling active power of series-compensated FACTS devices and low voltages at buses have been solved by controlling reactive power of shunt-compensated FACTS devices. Especially, Especially, UPFC has been applied in both line congestion and low voltages. Two kinds of indices which indicate the power system security level related to line flow and bus voltage are utilized in this paper. They have been minimized to enhance the power system security level through the iterative method and the sensitivity vector of security index is derived to determine the direction to minimum. The proposed algorithm has been tested on the IEEE 57-bus system with FACTS devices in a normal condition and a line-faulted contingency.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.59 no.4
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• pp.372-376
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• 2010

Electrolytic capacitors have been widely used in power electronics system because of the features of large capacitance, small size, high-voltage, and low-cost. Electrolytic capacitors, which is most of the time affected by aging effect, plays a very important role for the power electronics system quality and reliability. Therefore it is important to estimate the parameter of an electrolytic capacitor to predict the failure. The estimation of the equivalent series resistance(ESR) is important parameter in life condition monitoring of electrolytic capacitor. This paper proposes a simple technique to measure the ESR of an electrolytic capacitor. This method uses a switching DC/DC boost converter to measure the DC Bus capacitor ESR of power converter. Main advantage of the proposed method is very simple in technique, consumes very little time and requires only simple instruments. Simulation results are shown to verify the performance of the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.1-6
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• 2009

This paper presents new high speed architecture using DBI(Data Bus Inversion) in DRAM. The DBI is one of the general methods in the signaling circuits to decrease the known problems such as SSO and LSI. Many architectures have been proposed to reduce the number of transitions on the data bus. In this paper, the DBI, the Analog Majority Voter (AMV) circuit, the GIO control circuit and the SSO algorithm are newly proposed. The power consumption can he reduced with the help of direct GIO inversion method and the eye diagram of data can be increased to 40ps. Using proposed DBI scheme can produce almost stable SI of DQs against high speed operation. The DBI is fabricated in 90nm CMOS Technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.93-98
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• 2004

A low power SRAM using elevated source level memory cells is proposed to save the write power of SRAM. It reduces the swing voltages of the bit lines and data bus by elevating the source level of the memory cells from GND to $V_{T}$ and lowering the precharge level of the bit lines and data bus from $V_{DD}$ to $V_{DD}$ - $V_{T}$. It saves the write power of SRAM without area overhead and speed degradation. An SRAM with 8K${\times}$32bits is fabricated in a 0.25um CMOS process. It saves 45% of the power in write cycles at 300MHz with 2.5V. The maximum operating frequency is 330MHz.

• Proceedings of the KIPE Conference
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• 2017.07a
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• pp.198-199
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• 2017

This paper proposed a new control method for supercapacitor (SC) to compensate the pulse load transient and enhance the power quality of dc microgrid. By coordinating the operation frequency, the supercapacitor is controlled to handle the surge current component while the low-frequency current component is dealt with by remaining sources in the system. Based on the state of charge and dc bus voltage level, the SC unit operation mode is automatically decided. Meanwhile, the dc bus voltage level indicates the power demand of the whole system; by regulating the dc bus voltage, the mismatch of power demand is covered by SC unit. The effectiveness of proposed method is verified by experiment prototype formed by two distributed generation and one supercapacitor unit.

• Proceedings of the KIEE Conference
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• 2001.05a
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• pp.7-9
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• 2001

Many developing countries has been voltage unstable and the inter- change capability in Korea is limited by voltage instability. In analyzing voltage stability, load model has been considered as constant power, but actual loads vary as voltage changes. In order to incorporating voltage-dependent load model. we need the low-side of P-V curve that can not be obtained by general load flow algorithm. This paper proposes a modified GCF algorithm to obtain a full low-side of P-V curve and a accurate voltage assessment index considering load model. 5-bus sample system and 19-bus real power system are applied to simulate the proposed GCF. Also. the effect of reactive power compensation is illustrated in same systems.