• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1881-1883
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• 2001

We manufactured a micro CPL by LlGA process, a new conceptual ultra-fine and precise forming method, using X-ray lithography process. We fabricated a BN X-ray mask having properties of good X-ray transmittance and large mechanical strength. Micro CPL was manufactured by dividing into an upper plate and a low plate. Each of plates was bonded by Ag paste screen printing. The upper plate was fabricated on glass wafer to observe flow and phase transformation of cooling solution. The lower plate was manufactured by Cu electroplating for good heat transmission. Precision of inner Parts, micro pin and micro channel, of manufactured micro CPL is under ${\pm}2{\mu}m$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 춘계학술대회 논문집 반도체 재료 센서 박막재료 전자세라믹스
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• pp.121-124
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• 2004

The research on the porous silicon having low wafer stress during the oxidation process in IPOS(Isolation by Porous Oxidized Silicon) were carried out. Fine pores with less than 100A of diameter were found in the porous silicon which from p-type Si by electrochemical etching. In this study, it is possible to make the porous silicon with 59% of porosity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1816-1818
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• 1996

A micro-size nonthermal plasma generator, using a $SiO_2$ film as a dielectric barrier, has been studied experimentally for a high frequency ac voltage in 2LPM oxygen gas fed. The $SiO_2$ film as a micro-size dielectric barrier was made by the wet oxidation of n-type Si wafer($220[{\mu}mt]$). It can be generated ozone, as a nonthermal plasma intensity parameter, at very low level of applied voltage about 1[kV] by using the micro-size dielectric barrier. As a result, in case that have no air gap spacing i.e. surface discharge case shows relatively higher ozone concentration rather than that case of the micro-airgap spacing.

• 센서학회지
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• 제13권3호
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• pp.175-181
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• 2004

A pressure sensor for high temperature was fabricated by using a SDB(Silicon-Direct-Bonding) wafer with a Si/$SiO_{2}$/ Si structure. High pressure sensitivity was shown from the sensor using a single crystal silicon of the first layer as a piezoresistive layer. It also was made feasible to use under the high temperature as of over $120^{\circ}C$, which is generally known as the critical temperature for the general silicon sensor, by isolating the piezoresistive layer dielectrically and thermally from the silicon substrate with a silicon dioxide layer of the second layer. The pressure sensor fabricated in this research showed very high sensitivity as of $183.6{\mu}V/V{\cdot}kPa$, and its characteristics also showed an excellent linearity with low hysteresis. This sensor was usable up to the high temperature range of $300^{\circ}C$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.555-556
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• 2007

Through the single head kinematics, sliding distance is a movement of a pad within wafer. The sliding distance is very important to frictional heat, material removal, and so on. A Temperature distribution is similar to sliding distance. But is not same. Because of complex process factor in CMP. A platen velocity is a dominant factor in a temperature and material removal. WIWNU is low in head faster condition.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.558-559
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• 2007

A commercially de-waxer which kinds of solvent after was used to remove a thick organic wax film after polishing process and several steps of SC-1 cleanings were followed for the removal of organic wax residues and particles which requires long process time and high cost of ownership (COO). DIO3 was used to remove organic wax residues too achieve low COO. In this study, 0103 rinsing could use instead of 01 water rinsing. The process time and chemical consumption were reduced by using DIO3.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.57-58
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• 2006

Chemical-mechanical planarization (CMP) of Cu has used currently in semiconductor process for multilevel metallization system. This process requires the application of a considerable down-pressure to the sample in the polishing, because porous low-k films used in the Cu-multilevel interconnects of 65nm technology node are often damaged by mechanical process. Also, it make possible to reduce scratches and contaminations of wafer. Electrochemical mechanical planarization (ECMP) is an emerging extension of CMP. In this study, the electrochemical mechanical polisher was manufactured. And the static and dynamic potentiodynamic curve of Cu were measured in KOH based electrolyte and then the suitable potential was found.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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• pp.1291-1293
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• 2005

Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

• 한국전기전자재료학회논문지
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• 제24권4호
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• pp.328-332
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• 2011

The formation of front metal contact silicon solar cells is required for low cost, low contact resistance to silicon surface. One of the front metal contacts is Ni/Cu plating that it is available to simply and inexpensive production to apply mass production. Ni is shown to be a suitable barrier to Cu diffusion into the silicon. The process of Ni electroless plating on front silicon surface is performed using a chemical bath. Additives and buffer agents such as ammonium chloride is added to maintain the stability and pH control of the bath. Ni deposition rate is found to vary with temperature, time, utilization of bath. The experimental result shown that Ni layer by SEM (scanning electron microscopy) and EDX analysis. Finally, plated Ni/Cu contact solar cell result in an efficiency of 17.69% on $2{\times}2\;cm^2$, Cz wafer.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2000년도 춘계학술대회 논문집
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• pp.1051-1054
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• 2000

We developed the micro CSF (celebrospinal fluid) shunt valve with surface and bulk micromachining technology in polymer MEMS. This micro CSF shunt valve was formed with four micro check valves to have a membrane connected to the anchor with the four bridges. The up-down movement of the membrane made the CSF on & off and the valve characteristic such as open pressure was controlled by the thickness and shape of the bridge and the membrane. The membrane, anchor and bridge layer were made of the $O_2$ RIE (reactive ion etching) patterned Parylene thin film to be about 5~10 microns in thickness on the silicon wafer. The dimension of the rectangular nozzle is 0.2＊0.2 $\textrm{mm}^2$ and the membrane 0.45 mm in diameter. The bridge width is designed variously from 0.04 mm to 0.12 mm to control the valve characteristics. To protect the membrane and bridge in the CSF flow, we developed the packaging system for the CSF micro shunt valve with the deep RIE of the silicon wafer. Using this package, we can control the gap size between the membrane and the nozzle, and protect the bridge not to be broken in the flow. The total dimension of the assembled system is 2.5＊2.5 $\textrm{mm}^2$ in square, 0.8 mm in height. We could precisely control the burst pressure and low rate of the valve varing the design parameters, and develop the whole CSF shunt system using this polymer MEMS fabricated CSF shunt valve.