• Title/Summary/Keyword: Low-frequency noise (1/f noise)

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A Basic Study on the Design of the GPS Receiver (GPS의 수신기 개발을 위한 기초연구)

  • 정세모;정규형
    • Journal of the Korean Institute of Navigation
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    • v.6 no.1
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    • pp.1-18
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    • 1982
  • In this paper, author studied on the elementary data required for the design of the receiver of Pseudo Noise (PN) phase modulation communication adopted in Global Positioning System(GPS). By computer simulation technique, the phase modulator, filters, and PN generator are designed, and also required bandwidth of R-F amplifier for carrier frequency in phase modulation system is investigated. It is verified that the optimum bandwidth is about 3 times of the PN frequency and almost independent of the carrier frequency. And the low pass filter required for demodulation of slow Boolean data is also found to be about 60 times of the data signal frequency.

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W-band Single-chip Receiver MMIC for FMCW Radar (FMCW 레이더용 W-대역 단일칩 수신기 MMIC)

  • Lee, Seokchul;Kim, Youngmin;Lee, Sangho;Lee, Kihong;Kim, Wansik;Jeong, Jinho;Kwon, Youngwoo
    • Journal of the Institute of Electronics and Information Engineers
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    • v.49 no.10
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    • pp.159-168
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    • 2012
  • In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

A Design of Instrumentation Amplifier using a Nested-Chopping Technique (Nested-chopping 기법을 이용한 Instrumentation Amplifier 설계)

  • Lee, Jun-Gyu;Burm, Jin-Wook;Lim, Shin-Il
    • Proceedings of the KIEE Conference
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    • 2007.10a
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    • pp.483-484
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    • 2007
  • In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

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5.8 GHz PLL using High-Speed Ring Oscillator for WLAN (WLAN을 위한 고속 링 발진기를 이용한 5.8 GHz PLL)

  • Kim, Kyung-Mo;Choi, Jae-Hyung;Kim, Sam-Dong;Hwang, In-Seok
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.45 no.2
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    • pp.37-44
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    • 2008
  • This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

LNA with Chopper Stabilization Technique Using Sample and Hold Circuit (샘플 홀드 회로를 이용한 초퍼 안정화 기법이 적용된 저잡음 증폭기)

  • Park, Youngmin;Nam, Minho;Cho, Kyoungrok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.27-33
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    • 2016
  • This paper proposes a Low Noise Amplifier (LNA) with chopper stabilization technique with a sample-hold circuit. Chopper stabilization technique is effective in terms of reducing low frequency offset and flicker noise. Conventional chopper amplifier has a disadvantage in area because of using Low Pass Filter (LPF) for remove chopping spike. The proposed chopper amplifier employed sample and hold technique to decrease chopping spike instead of LPF that improves 36% in voltage damping and 11% in area.

Noise Characteristics of 64-channel 2nd-order DROS Gradiometer System inside a Poorly Magnetically-shielded Room (저성능 자기차폐실에서 64채널 DROS 2차 미분계 시스템의 잡음 특성)

  • Kim, J.M.;Lee, Y.H.;Yu, K.K.;Kim, K.;Kwon, H.;Park, Y.K.;Sasada, Ichiro
    • Progress in Superconductivity
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    • v.8 no.1
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    • pp.33-39
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    • 2006
  • We have developed a second-order double relaxation oscillation SQUID(DROS) gradiometer with a baseline of 35 mm, and constructed a poorly magnetically-shielded room(MSR) with an aluminum layer and permalloy layers for magnetocardiography(MCG). The 2nd-order DROS gradiometer has a noise level of 20 $fT/{\surd}Hz$ at 1 Hz and 8 $fT/{\surd}Hz$ at 200 Hz inside the heavily-shielded MSR with a shielding factor of $10^3$ at 1 Hz and $10^4-10^5$ at 100 Hz. The poorly-shielded MSR, built of a 12-mm-thick aluminum layer and 4-6 permalloy layers of 0.35 mm thickness, is 2.4mx2.4mx2.4m in size, and has a shielding factor of 40 at 1 Hz, $10^4$ at 100 Hz. Our 64-channel second-order gradiometer MCG system consists of 64 2nd-order DROS gradiometers, flux-locked loop electronics, and analog signal processors. With the 2nd-order DROS gradiometers and flux-locked loop electronics installed inside the poorly-shielded MSR, and with the analog signal processor installed outside it, the noise level was measured to be 20 $fT/{\surd}Hz$ at 1 Hz and 8 $fT/{\surd}Hz$ at 200 Hz on the average even though the MSR door is open. This result leads to a low noise level, low enough to obtain a human MCG at the same level as that measured in the heavily-shielded MSR. However, filters or active shielding is needed fur clear MCG when there is large low-frequency noise from heavy air conditioning or large ac power consumption near the poorly-shielded MSR.

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Measurement of Nonlinear Propagation Characteristics of Vibration in the Tissue Using Bispectral Analysis (바이스펙트럼 해석을 이용한 생체조직 내에서의 진동의 비선형 전파특성 계측)

  • ;lgo
    • Journal of Biomedical Engineering Research
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    • v.14 no.1
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    • pp.31-40
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    • 1993
  • It is well known that nonlinear propagation characteristics of the wave in the tissue may give very useful information for the medical diagnoisis. In this paper, a new method to detect nonlinear propa gation characteristics of the internal vibration in the tissue for the low frequency mechanical vibra lion by using bispectral analysis is proposed. In the method, low frequency vibration of $f_0(=100Hz)$ is applied on the surface of the object, and the waveform of the internal vibration ${\times}{\;}(t)$ is measured from Doppler frequency modulation of silmultaneously transmitted probing ultrasonic waves. Then, the bispectra of the signal ${\times}{\;}(t.)$ at the frequencies ($f_0,{\;}f_0$) and ($f_0,{\;}2f_0$) are calculated to estimate the nonlinear propagation characteristics as their magnitude ratio, where since bispectrum is free from the gallssian additive noise we can get the value with high S/N. Basic experimental system is con structed by using 3.0 MHz probing ultrasonic waves and the several experiments are carried out for some phantoms. Results show the superiority of the proposed method to the conventional method using power spectrum and also its usefulness for the tissue characterization.

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Design of a Low-Power CMOS Fractional-N Frequency Synthesizer for 2.4GHz ISM Band Applications (2.4GHz ISM 대역 응용을 위한 저전력 CMOS Fractional-N 주파수합성기 설계)

  • Oh, Kun-Chang;Kim, Kyung-Hwan;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.60-67
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    • 2008
  • A low-power 2.4GHz fractional-N frequency synthesizer has been designed for 2.4GHz ISM band applications such as Bluetooth, Zigbee, and WLAN. To achieve low-power characteristic, the design has been focused on the power optimization of power-hungry blocks such as VCO, prescaler, and ${\Sigma}-{\Delta}$ modulator. An NP-core type VCO is adopted to optimize both phase noise and power consumption. Dynamic D-F/Fs with no static DC current are employed in designing the low-power prescaler circuit. The ${\Sigma}-{\Delta}$ modulator is designed using a modulus mapping circuit for reducing hardware complexity and power consumption. The designed frequency synthesizer which was fabricated using a $0.18{\mu}m$ CMOS process consumes 7.9mA from a single 1.8V supply voltage. The experimental results show that a phase noise of -118dBc/Hz at 1MHz offset, the reference spur of -70dBc at 25MHz offset, and the channel switching time of $15{\mu}s$ over 25MHz transition have been achieved. The designed chip occupies an area of $1.16mm^2$ including pads where the core area is only $0.64mm^2$.

Design of Quadrature CMOS VCO using Source Degeneration Resistor (소스 궤환 저항을 이용한 직교 신호 발생 CMOS 전압제어 발진기 설계)

  • Moon Seong-Mo;Lee Moon-Que;Kim Byung-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.12 s.91
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    • pp.1184-1189
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    • 2004
  • A new schematic of quadrature voltage controlled oscillator(QVCO) is designed and fabricated. To obtain quadrature characteristic and low phase noise simultaneously, two differential VCOs are forced to un in quadrature mode by using coupling amplifier with a source degeneration resistor, which is optimized to obtain quadrature accuracy with minimum phase noise degradation. The designed QVCO was fabricated in standard CMOS technology. The measured performance showed the phase noise of below -120 dBc/Hz at 1 MHEz frequency offset, tuning bandwidth of 210 MHz from 2.34 GHz to 2.55 GHz with a tuning voltage varying form 0 to 1.8 V Quadrature error of 0.5 degree and amplitude error of 0.2 dB was measured with conjunction with low-lF mixer. The fabricated QVCO requires 19 mA including 5 mA in the VCO core part fiom a 1.8 V supply.

Studies on the High-gain Low Noise Amplifier for 60 GHz Wireless Local Area Network (60 GHz 무선 LAN의 응용을 위한 고이득 저잡음 증폭기에 관한 연구)

  • 조창식;안단;이성대;백태종;진진만;최석규;김삼동;이진구
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.11
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    • pp.21-27
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    • 2004
  • In this paper, millimeter-wave monolithic integrated circuit(MIMIC) low noise amplifier(LNA) for V-band, which is applicable to 60 GHz wireless local area network(WLAN), was fabricated using the high performance 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-gate pseudomorphic high electron mobility transistor(PHEMT). The DC characteristics of PHEMT are drain saturation current density(Idss) of 450 mA/mm and maximum transconductance(gm, max) of 363.6 mS/mm. The RF characteristics were obtained the current gain cut-off frequency(fT) of 113 GHz and the maximum oscillation frequency(fmax) of 180 GHz. V-band MIMIC LNA was designed using active and passive device library, which is composed of 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-gate PHEMT and coplanar waveguide(CPW) technology. The designed V-band MIMIC LNA was fabricated using integrated unit processes of active and passive device. The measured results of V-band MIMIC LNA are shown S21 gain of 21.3 dB, S11 of -10.6 dB at 60 GHz and S22 of -29.7 dB at 62.5 GHz. The measured result of V-band MIMIC LNA was shown noise figure (NF) of 4.23 dB at 60 GHz.