• 한국통신학회논문지
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• 제35권7C호
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• pp.611-617
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• 2010

본 논문에서는 직렬 연접 길쌈 부호와 LDPC 부호를 이용하여 수직자기기록 채널에서의 성능을 조사하였다. 실험과정에서 기록 밀도는 1.7, 2.0, 2.4, 2.8 일 때를 각각 실험하였다. 직렬 연접 길쌈 부호는 LDPC 부호보다 복호기의 구현 복잡도가 더 낮다. 직렬 연접 부호는 순환 구조적 길쌈 부호의 부호기와 복호기, 그리고 프리코더와 인터리버로 이루어져 있다. 본 실험에서 직렬 연접 길쌈 부호의 복호 알고리즘은 메시지 전달 알고리즘을 이용하였으며, LDPC 부호의 복호 알고리즘은 Sum Product 알고리즘을 이용하였다. 신호 검출기와 오류정정부호 사이에 반복 복호 기법을 적용한 터보등화기 기법을 적용하였고, 기록 밀도가 높아짐에 따라 직렬 연접 길쌈 부호가 LDPC 부호 보다 더 효율 적인 것을 보였다.

• 한국통신학회논문지
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• 제32권4C호
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• pp.370-378
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• 2007

The most appropriate low density parity check (LDPC) code for hybrid automatic repeat request (HARQ) system suitable for future multimedia communication systems is presented in this paper. HARQ system with punctured LDPC code is investigated at first. And two transmission schemes with parallel concatenated LDPC code are also presented and their performances are analyzed according to the various values of mean column weight (MCW). As a result, the parallel concatenated LDPC code with the diversity effect of information bit is considered to be more appropriate for HARQ system considering the throughput as well as error performance.

• ETRI Journal
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• 제34권4호
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• pp.629-632
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• 2012

This letter investigates the combination of the Chase-2 and sum-product (SP) algorithms for low-density parity-check (LDPC) codes. A simple modification of the tanh rule for check node update is given, which incorporates test error patterns (TEPs) used in the Chase algorithm into SP decoding of LDPC codes. Moreover, a simple yet effective approach is proposed to construct TEPs for dealing with decoding failures with low-weight syndromes. Simulation results show that the proposed algorithm is effective in improving both the waterfall and error floor performance of LDPC codes.

• Journal of Communications and Networks
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• 제11권6호
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• pp.538-543
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• 2009

A wiretap channel I is one of the channel models that was proved to achieve unconditional security. However, it has been an open problem in realizing such a channel model in a practical network environment. The paper is committed to solve the open problem by introducing a novel approach for building wiretap channel I in which the eavesdropper sees a binary symmetric channel (BSC) with error probability p while themain channel is error free. By taking advantage of the feedback and low density parity check (LDPC) codes, our scheme adds randomness to the feedback signals from the destination for keeping an eavesdropper ignorant; on the other hand, redundancy is added and encoded by the LDPC codes such that a legitimate receiver can correctly receive and decode the signals. With the proposed approach, unconditionallysecure communication can be achieved through interactive communications, in which the legitimate partner can realize the secret information transmission without a pre-shared secret key even if the eavesdropper has better channel from the beginning.

• 대한전자공학회논문지SD
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• 제43권9호
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• pp.31-37
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• 2006

Low Density Parity Check (LDPC) code는 최근 그 우수한 성능으로 인하여 4세대 무선 이동 통신용 채널 코딩으로 주목받고 있다. 또한 유럽 디지털 위성 방송 규격인 DVB-S2는 LDPC 코드를 채널 코딩방식으로 채택하였다. 본 논문에서는 인코더와 디코더 양쪽 모두 효율적으로 하드웨어 구현이 가능한 hybrid H-matrix 구조를 이용한 DVB-S2 LDPC 복호기 구조를 제안한다. Hybrid H-matrix는 semi-random 방식과 partly parallel 방식을 결합하여 부호기와 복호기를 동시에 효율적으로 구현할 수 있다. 제안된 복호기 구조에서는 다양한 코드율에 사용되는 Variable Node processor Unit (VNU)을 재사용하기 위한 새로운 VNU와 최적화된 블록 메모리 배치 방법을 이용하였다. 제안된 구조를 이용하여 코드율 1/2의 DVB-S2 LDPC 복호기를 설계하였고 그 결과를 기존의 복호기와 비교하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• Journal of Communications and Networks
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• 제16권5호
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• pp.479-484
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• 2014

In this paper, we consider the construction of cyclic and quasi-cyclic structured q-ary low-density parity-check (LDPC) codes over a designated small field. The construction is performed with a pre-defined sliding-window, which actually executes the regular mapping from original field to the targeted field under certain parameters. Compared to the original codes, the new constructed codes can provide better flexibility in choice of code rate, code length and size of field. The constructed codes over small fields with code length from tenths to hundreds perform well with q-ary sum-product decoding algorithm (QSPA) over the additive white Gaussian noise channel and are comparable to the improved spherepacking bound. These codes may found applications in wireless sensor networks (WSN), where the delay and energy are extremely constrained.

• 대한임베디드공학회논문지
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• 제11권6호
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• pp.325-334
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• 2016

Recently, Open Computing Language (OpenCL) has been proposed to provide a framework that supports heterogeneous computing platforms. By using an OpenCL framework, digital communication systems can support various protocols in a unified computing environment to achieve both high portability and high performance. This article introduces a parallel software decoder of Low Density Parity Check (LDPC) codes for China Multimedia Mobile Broadcasting (CMMB) on a heterogeneous platform. Each step of LDPC decoding has different parallelization characteristics. In this paper, steps suitable for task-level parallelization are executed on the CPU, and steps suitable for data-level parallelization are processed by the GPU. To improve the performance of the proposed OpenCL kernels for LDPC decoding operations, explicit thread scheduling, loop-unrolling, and effective data transfer techniques are applied. The proposed LDPC decoder achieves high performance by using heterogeneous multi-core processors on a unified computing framework.

• 대한전자공학회논문지SP
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• 제44권1호
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• pp.76-84
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• 2007

본 논문에서는 워터마크 예측과 LDPC 코드를 이용하여 워터마크의 성능을 향상시키는 알고리듬을 제안한다. 워터마크 추출의 경우 삽입된 워터마크의 파워(power)가 원본 영상의 파워에 비해 아주 작기 때문에 워터마크의 추출 성능을 높이기 위해서는 워터마크의 예측이 필수적이다. 본 논문에서는 웨이블릿 영역에서 잡음 제거 필터를 사용하여 워터마크의 예측을 수행하였다. 이렇게 예측된 워터마크에 에러가 발생할 경우 LDPC 코드를 사용하여 수정하였다. 에러 수정 시 삽입된 워터마크의 통계적인 특성을 사용하여 기존의 LDPC 코드의 성능보다 우수한 실험 결과를 도출하였다.

• ETRI Journal
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• 제37권1호
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.