• Title/Summary/Keyword: Low-density parity-check(LDPC) decoder

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An Architecture for IEEE 802.11n LDPC Decoder Supporting Multi Block Lengths (다중 블록길이를 지원하는 IEEE 802.11n LDPC 복호기 구조)

  • Na, Young-Heon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2010.05a
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    • pp.798-801
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    • 2010
  • This paper describes an efficient architecture for LDPC(Low-Density Parity Check) decoder, which supports three block lengths (648, 1,296, 1,944) of IEEE 802.11n standard. To minimize hardware complexity, the min-sum algorithm and block-serial layered structure are adopted in DFU(Decoding Function Unit) which is a main functional block in LDPC decoder. The optimized H-ROM structure for multi block lengths reduces the ROM size by 42% as compared to the conventional method. Also, pipelined memory read/write scheme for inter-layer DFU operations is proposed for an optimized operation of LDPC decoder.

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Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix

  • Lee, Chan-Ho
    • ETRI Journal
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    • v.27 no.5
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    • pp.557-562
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    • 2005
  • Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

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An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

  • Byun, Yong Ki;Park, Jong Kang;Kwon, Soongyu;Kim, Jong Tae
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.1
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    • pp.8-14
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    • 2013
  • A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

Low-Complexity Multi-Size Circular Shifter for QC-LDPC Decoder Based on Two Serial Barrel-Rotators (두 개의 직렬 Barrel-Rotator를 이용한 QC-LDPC 복호기용 저면적 Multi-Size Circular Shifter)

  • Kang, Hyeong-Ju
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.8
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    • pp.1839-1844
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    • 2015
  • The low-density parity-check(LDPC) code has been adopted in many communication standards due to its error correcting performance, and the quasi-cyclic LDPC(QC-LDPC) is widely used because of implementation easiness. In the QC-LDPC decoder, a cyclic-shifter is required to rotate data in various sizes. This kind of cyclic-shifters are called multi-size circular shifter(MSCS), and this paper proposes a low-complexity structure for MSCS. In the conventional serially-placed two barrel-rotators, the unnecessary multiplexers are revealed and removed, leading to low-complexity. The experimental results show that the area is reduced by about 12%.

Design of Low-Density Parity-Check Codes for Multiple-Input Multiple-Output Systems (Multiple-Input Multiple-output system을 위한 Low-Density Parity-Check codes 설계)

  • Shin, Jeong-Hwan;Chae, Hyun-Do;Han, In-Duk;Heo, Jun
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.7C
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    • pp.587-593
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    • 2010
  • In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) system, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are optimal maximum a posteriori probability (MAP) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel.

Decoding Method of LDPC Codes in IEEE 802.16e Standards for Improving the Convergence Speed (IEEE 802.16e 표준에 제시된 LDPC 부호의 수렴 속도 개선을 위한 복호 방법)

  • Jang, Min-Ho;Shin, Beom-Kyu;Park, Woo-Myoung;No, Jong-Seon;Jeon, In-San
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.12C
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    • pp.1143-1149
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    • 2006
  • In this paper, the modified iterative decoding algorithm[8] by partitioning check nodes is applied to low-density parity-check(LDPC) codes in IEEE 802.16e standards, which gives us the improvement for convergence speed of decoding. Also, the new method of check node partitioning which is suitable for decoding of the LDPC codes in IEEE 802.16e system is proposed. The improvement of convergence speed in decoding reduces the number of iterations and thus the computational complexity of the decoder. The decoding method by partitioning check nodes can be applied to the LDPC codes whose decoder cannot be implemented in the fully parallel processing as an efficient sequential processing method. The modified iterative decoding method of LDPC codes using the proposed check node partitioning method can be used to implement the practical decoder in the wireless communication systems.

Code Rate 1/2, 2304-b LDPC Decoder for IEEE 802.16e WiMAX (IEEE 802.16e WiMAX용 부호율 1/2, 2304-비트 LDPC 복호기)

  • Kim, Hae-Ju;Shin, Kyung-Wook
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.4A
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    • pp.414-422
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    • 2011
  • This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

Design of Low-Density Parity-Check Codes for Multi-Input Multi-Output Systems (Multi-Input Multi-Output System을 위한 Low-Density Parity-Check codes 설계)

  • Shin, Jeong-Hwan;Heo, Jun
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.161-162
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    • 2008
  • In this paper we design an irregular low-density parity-check (LDPC) code for a multi-input multi-output (MIMO) system. The considered MIMO system is minimum mean square error soft-interference cancellation (MMSE-SIC) detector. The MMSE-SIC detector and the LDPC decoder exchange soft information and consist a turbo iterative detection and decoding receiver. Extrinsic information transfer (EXIT) charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the input-output transfer chart of the MMSE-SIC detector. It is shown that the performance of the designed LDPC code is much better than that of conventional LDPC code optimized for the AWGN channel.

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Design of an Efficient LDPC Codec for Hardware Implementation (하드웨어 구현에 적합한 효율적인 LDPC 코덱의 설계)

  • Lee Chan-Ho;Park Jae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.7 s.349
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    • pp.50-57
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    • 2006
  • Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and compared with the previous results.

Progressive Edge-Growth Algorithm for Low-Density MIMO Codes

  • Jiang, Xueqin;Yang, Yi;Lee, Moon Ho;Zhu, Minda
    • Journal of Communications and Networks
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    • v.16 no.6
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    • pp.639-644
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    • 2014
  • In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.