• Journal of the Architectural Institute of Korea Planning & Design
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• v.35 no.10
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• pp.71-82
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• 2019

This study tried to prove why a low-rise residential block is more vitalized than in a superblock consisted of an apartment housing complex. To do this, two adjacent superblocks in Yeoksam 2-dong were selected as a case study among superblocks of residential area in Gangnam, Seoul. It adopted the concept of 'complexity', 'Osmosis', 'Vitality' and 'Permeability' for evaluation indexes to measure street vitality. As a result, four indexes were clearly higher in low-density residential superblocks than apartment housing complex superblocks. First, the superblocks for apartment housing complexes showed a lower 'complexity' because large-scale parcels for an apartment housing complex reduces a possibility for various land uses. Second, smaller blocks improved "osmosis" compared to larger blocks, and the larger the block, the less likely it is that buildings and streets penetrate activity. Third, as the apartment complex block became larger, the number of accesses decreased. Thus, it did not provide vitality to the streets. Fourth, high permeability was shown in the low-density superblocks, while that of the superblock consisted of apartment housing complexes was very low because the entrance of the complexes entrance is closed to the public. The results of this study demonstrated that an apartment housing complex may hamper street vitality and deteriorate the quality of urban environments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.29-40
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• 2008

The efficient hardware design of finite field multiplication is an very important research topic for and efficient $f(x)=x^n+x^k+1$ implementation of cryptosystem based on arithmetic in finite field GF($2^n$). We used special generating trinomial to construct a bit-parallel multiplier over finite field with low space complexity. To reduce processing time, The hardware architecture of proposed multiplier is similar with existing Mastrovito multiplier. The complexity of proposed multiplier is depend on the degree of intermediate term $x^k$ and the space complexity of the new multiplier is $2k^2-2k+1$ lower than existing multiplier's. The time complexity of the proposed multiplier is equal to that of existing multiplier or increased to $1T_X(10%{\sim}12.5%$) but space complexity is reduced to maximum 25%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.48 no.5
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• pp.123-128
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• 2011

In this paper, we design the CA-CFAR processor using a root-square approximation approach and a fixed-point operation to improve hardware complexity and reduce computational effort. We also propose CA-CFAR processor with multi-window, which is capable of concurrent parallel processing. The proposed architecture is synthesized and implemented into the FPGA and the performance is compared with the conventional processor designed by root-square libarary licensed by FPGA corporation.

• KIISE Transactions on Computing Practices
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• v.20 no.10
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• pp.561-566
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• 2014

There are growing demands for improving the patient safety and the effectiveness of medical services through device connectivity and interoperability. However, integration through networking might greatly increase the complexity of the system if it is not properly designed, jeopardizing patient safety. In this paper, we codify safe medical device interaction patterns, and exploit them for the low complexity design and safety analysis of networked supervisory medical systems. We implement the proposed approach as a plug-in of Architecture Analysis and Description Language (AADL). Our implementation enables the modeling and safety analysis of medical devices and their interactions before actual development.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.625-634
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• 2002

Cryptography is the methods of making and using secret writing that is necessary to keep messages private between two parties. Cryptography is compute-intensive algorithm and needs cpu resource excessively. To solve these problems, there exists hardware approach that implements cryptographic algorithm with hardware chip. In this paper, we presents the design and implementation of cryptographic hardware and compares its performance with software cryptographic algorithms. The experimental result shows that the hardware approach causes high I/O overheads when it transmits data between cryptographic board and host cpu. Hence, low complexity cryptographic algorithms such as DES does not improve the performance. But high complexity cryptographic algorithms such as Triple DES improve the performance with a high rate, roughly from two times to Sour times.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.490-490
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• 2006

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2003.07a
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• pp.33-36
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• 2003

본 논문에서는 GF(2$^{m}$ ) 상에서 효율적인 공간 복잡도를 가진 LFSR(Linear Feedback Shift Register) 구조 기반의 모듈러 곱셈기를 제안한다. 제안된 구조는 기약다항식으로 모든 계수가 1인 속성의 AOP(All One Polynomial)를 이용한다. 제안된 구조는 구조복잡도 면에서 기존의 구조들보다 훨씬 효율적이다. 제안된 곱셈기는 공개키 암호의 기본 구조로 사용될 수 있다.

• Advances in Computational Design
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• v.1 no.1
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• pp.87-103
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• 2016

This paper adopts and investigates the non-dominated sorting approach for extending the single-objective Cuckoo Search (CS) into a multi-objective framework. The proposed approach uses an archive composed of primary and secondary population to select and keep the non-dominated solutions at each generation instead of pairwise analogy used in the original Multi-objective Cuckoo Search (MOCS). Our simulations show that such a low computational complexity approach can enrich CS to incorporate multi-objective needs instead of considering multiple eggs for cuckoos used in the original MOCS. The proposed MOCS is tested on a set of multi-objective optimization problems and two well-studied engineering design optimization problems. Compared to MOCS and some other available multi-objective algorithms such as NSGA-II, our approach is found to be competitive while benefiting simplicity. Moreover, the proposed approach is simpler and is capable of finding a wide spread of solutions with good coverage and convergence to true Pareto optimal fronts.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11B
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• pp.965-971
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• 2003

This paper suggests a low-complexity frame timing synchronization system for IEEE802.11a wireless LAN systems. The proposed timing synchronization scheme has been implemented by correlating the received OFDM preamble with quantized coefficients composed of ｛0, ${\pm}$2$^{0}$ , ${\pm}$2$^1$‥‥‥ ${\pm}$2$^{i}$ ), where i is an integer number. The 2$^{i}$ -valued coefficients enable the multipliers in the correlation system to be simplified to i-bit shifters. So we can design the correlation system using shifters instead of multipliers. We estimate the performance of the proposed scheme in comparison with conventional systems under the AWGN and Rayleigh fading channels. In this paper we show that the complexity can be reduced by 90% while still maintaining a performance comparable to that of the conventional system.

• Journal of Communications and Networks
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• v.18 no.6
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• pp.913-925
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• 2016

In-band wireless full-duplex is a promising technology that enables a wireless node to transmit and receive at the same time on the same frequency band. Due to the complexity of self-interference cancellation techniques, only base stations (BSs) are expected to be full-duplex capable while user terminals remain as legacy half-duplex nodes in the near future. In this case, two different nodes share a single subchannel, one for uplink and the other for downlink, which causes inter-node interference between them. In this paper, we investigate the joint problem of subchannel assignment and power allocation in a single-cell full-duplex orthogonal frequency division multiple access (OFDMA) network considering the inter-node interference. Specifically, we consider two different scenarios: i) The BS knows full channel state information (CSI), and ii) the BS obtains limited CSI through channel feedbacks from nodes. In the full CSI scenario, we design sequential resource allocation algorithms which assign subchannels first to uplink nodes and then to downlink nodes or vice versa. In the limited CSI scenario, we identify the overhead for channel measurement and feedback in full-duplex networks. Then we propose a novel resource allocation scheme where downlink nodes estimate inter-node interference with low complexity. Through simulation, we evaluate our approaches for full and limited CSIs under various scenarios and identify full-duplex gains in various practical scenarios.