• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2010년도 하계학술대회 논문집
• /
• pp.161-161
• /
• 2010

In order to achieve low power consumption and the uniform power spectrum of LED BLU (Back Light Unit) system, new circuits with a 2 stage L-C (Inductor-Capacitor) coupler have been proposed. From the simulation results based on our proposed model, the ripple power of the L-C regulation-embedded BLU circuit shows a dramatic reduction by more than 89.3% as compared to the normal BLU (without L-C circuits). This indicates that the proposed circuit is very promising for the realization of high-efficiency BLU circuits.

• 전자공학회논문지B
• /
• 제31B권8호
• /
• pp.172-180
• /
• 1994

Implantable biotelemetry systems are indispensable tools not only in animal research but also in clinical medicine as such systems enable the acquisition of otherwise unavailable physiological data. We present the manufacture of CMOS IC and its system for implantable multichannel biotelemeter system. The internal circuits of this system are designed not only to achieve as multiple functions and low power dissipation as possible but also to enable continuous measurement of physiological data. Its main functions are to enable continuous measurement of physiological data and to accomplish on-off power swiching of an implantable battery by receiving appropriate commanc signals from an external circuit. The implantable circuits of this system are designed and fabricated on a single silicon chip using $1.5\mu$m n-well CMOS process technology. The total power dissipation of implantable circuits for a continuous operation was 6.7mW and for a stand-by operation was 15.2$\mu$ W. This system used together with approriate sensors is expected to contribute to clinical medicine telemetry system of measuring and wireless transmitting such significant physiological parameters as pressure pH and temperature.

• 센서학회지
• /
• 제27권6호
• /
• pp.362-367
• /
• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.125-128
• /
• 2001

In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.

• Journal of Electrical Engineering and information Science
• /
• 제2권6호
• /
• pp.28-35
• /
• 1997

A new approach concurrent transistor sizing and buffer insertion for low power optimization is proposed in this paper. The method considers the tradeoff between upsizing transistors and inserting buffers and chooses the solution with the lowest possible power and area cost. It operates by analyzing the feasible region of the cost-delay curves of the unbuffered and buffered circuits. As such the feasible region of circuits optimized by our method is extended to encompass the envelop of cost-delay curves which represent the union of the feasible regions of all buffered ad unbuffered versions of the circuit. The method is efficient and tunable in that optimality can be traded for compute time and as a result it can in theory near optimal results.

• ETRI Journal
• /
• 제44권5호
• /
• pp.837-848
• /
• 2022

Analog circuit design is comparatively more complex than its digital counterpart due to its nonlinearity and low level of abstraction. This study proposes a novel low-level hybrid of the sine-cosine algorithm (SCA) and modified grey-wolf optimization (mGWO) algorithm for machine learning-based design automation of CMOS analog circuits using an all-CMOS voltage reference circuit in 40-nm standard process. The optimization algorithm's efficiency is further tested using classical functions, showing that it outperforms other competing algorithms. The objective of the optimization is to minimize the variation and power usage, while satisfying all the design limitations. Through the interchange of scripts for information exchange between two environments, the SCA-mGWO algorithm is implemented and simultaneously simulated. The results show the robustness of analog circuit design generated using the SCA-mGWO algorithm, over various corners, resulting in a percentage variation of 0.85%. Monte Carlo analysis is also performed on the presented analog circuit for output voltage and percentage variation resulting in significantly low mean and standard deviation.

• Journal of Power Electronics
• /
• 제7권4호
• /
• pp.278-285
• /
• 2007

Recently, plasma display panels (PDP) have become the most promising candidate in the market for large screen size flat panel displays. PDPs have many merits such as a fast display response time and wide viewing angle. However, there are still concerns about high cost because they require complex driving circuits composed of high power switching devices to generate various voltage waveforms for three operational modes of reset, scan, and sustain. Conventional PDP driving circuits use path switches for voltage separation and a scan switch to offer a scan voltage for reset and scan operations, respectively. In addition, there exist reset switches to initialize PDPs by regulating the wall charge conditions with ramp shaped pulses, which means the necessity of specific power devices for the reset operation. Because power for the plasma discharge accompanied by a large current is transferred to a panel via path switches, high power rating switches are used for path switches. Therefore, this paper proposes a novel low-cost PDP driving scheme achieved by not only eliminating path switches but also merging the function of reset switches into other switches used for sustain or scan operations. The simulated voltage waveforms of the proposed topology and experimental results implemented in a 42-inch panel to demonstrate the validity of using a new gate driver that merges the functions of power switches are presented.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -2
• /
• pp.1192-1195
• /
• 2002

In this paper, we propose Low-Power Receiver circuits for a wireless communication system using ASK signal. Their structures are suitable for low supply current. The proposed circuits are designed and simulated by Spectre using 0.8m CMOS process parameters, and operate with supply current below 1.5${\mu}\textrm{A}$.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2007년도 하계종합학술대회 논문집
• /
• pp.433-434
• /
• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• 전기학회논문지P
• /
• 제62권2호
• /
• pp.84-89
• /
• 2013

In this paper, we propose interface circuits for reducing power consumption and EMI when sequences of data from LCD controller to LCD driver IC by transmitting two bit data during one clock period. The proposed circuits are operated in current mode, which is different from conventional voltage-mode signaling techniques, and also employ threshold technique of Modified-LVDS(Low Voltage Differential Signaling) method. We have simulated the proposed circuits using H-SPICE tool for performance analysis of the proposed method. The simulation results show that the proposed circuits provide a faster transmission speed and stronger noise immunity than the conventional LVDS circuits. It might be suitable for the real-time transmission of huge image data in LCD system.