• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.9
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• pp.667-670
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• 2010

In this paper, a high voltage current sensing circuit for boost converter is designed and verified by Cadence SPECTRE simulations. The current mirror pair, power and sensing metal-oxide semiconductor field effect transistors (MOSFETs) with size ratio of K, is used in our on-chip current sensing circuit. Very low drain voltages of the current mirror pair should be matched to give accurate current sensing, so a folded-cascode opamp with a PMOS input pair is used in our design. A high voltage high side lateral-diffused MOS transistor (LDMOST) switch is used between the current sensing circuit and power MOSFET to protect the current sensing circuit from the high output voltage. Simulation results using 0.35 ${\mu}m$ BCD process show that current sensing is accurate and the pulse frequency modulation (PFM) boost converter using the proposed current sensing circuit satisfies with the specifications.

• Journal of Power Electronics
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• v.15 no.3
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• pp.644-651
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• 2015

This paper introduces a novel digital one cycle control (DOCC) boost power factor correction (PFC) converter. The proposed PFC converter realizes the FPGA-based DOCC control approach for single-phase PFC rectifiers without input voltage sensing or a complicated two-loop compensation design. It can also achieve a high power factor and the operation of low harmonic input current ingredients over universal loads in continuous conduction mode. The trailing triangle modulation adopted in this approach makes the acquisition of the average input current an easy process. The controller implementation is based on a boost topology power circuit with low speed, low-resolution A/D converters, and economical FPGA development board. Experimental results demonstrate that the proposed PFC rectifier can obtain a PF value of up to 0.999 and a minimum THD of at least 1.9% using a 120W prototype.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1058-1061
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• 2002

This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

• Journal of Sensor Science and Technology
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• v.18 no.1
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• pp.95-101
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• 2009

A simple and new CMOS potentiostat circuit for amperometric sensor is described. To maintain a constant potential between the reference and working electrodes, only one differential difference amplifier (DDA) is needed in proposed design, while conventional potentiosatat requires at least 2 operational amplifiers and 2 resistors, or more than 3 operational amplifiers and 4 resistors for low voltage CMOS integrated potentiostat. The DDA with rail-to-rail design not only enables the full range operation to supply voltage but also provides simple potentiostat system with small hardwares and low power consumption.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.1853-1859
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• 2008

IGBT modules are designed for low loss, rugged for all environments and user friendly. Low on state saturation voltage with high switching speed is the primary concerns. In this paper selection of IGBT, module ratings and characteristics are discussed. The IGBT design topic of protection against over voltage and over current are covered. Emphasis on turn off switching, short circuit switching and necessary precautions are dealt. Selection of IGBT device, gate drive power, and its lay out considerations are covered in detail.

• Journal of Power Electronics
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• v.12 no.3
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• pp.458-467
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• 2012

Single phase converters suffer from ripple power pulsating at twice the line frequency. The ripple power is usually absorbed by a bulky capacitor bank and/or a dedicative LC resonant link, resulting in a low power density and a high cost. An alternative solution is using a dc link active power filter (APF) to direct the pulsating power into another energy-storage component. The main dc link filter capacitor can then be reduced substantially. Based on a mainstream dc APF topology, this paper proposed a new control strategy incorporating both dual-loop control and repetitive control. The circuit parameter design is also re-examined from a control point of view. The proposed APF scheme has better control performance, and is more suited for high power applications since it works in CCM and with a low switching frequency.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.158-162
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• 2002

This paper presents a novel 3-phase IGBT module called the SPM (Smart Power Module). This is a new design developed to provide a very compact, low cost, high performance and reliable motor drive system. Several distinct design concepts were used to achieve the highly integrated functionality in a new cost-effective small package. An overall description to the SPM is given and actual application issues such as electrical characteristics, circuit configurations, thermal performance and power ratings are discussed

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.139-141
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• 2019

Capacitive power transfer has an advantage in the simplicity of the energy link structure. So, the conventional phase -shift full bridge sometime is not always the best choice because of its complexity and high cost. On the other hand, the link capacitance is usually very low and requires high-frequency operation, but, the series resonant converter loses zero-voltage switching feature in the light load condition, which makes the switching loss high especially in CPT system. The paper proposes a new low-cost topology based on asymmetric half-bridge to achieve simplicity as well as wide zero voltage switching range. The design procedure is presented, and circuit operations are analyzed and verified by simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.8
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• pp.1-7
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• 1997

In ahigh power amplifier design, power combiner/divider is used to connect low power amplifiers in parallel. The raidal structure of the powe combiner/divider has not only a good characteristics of port-to-port isolation but also an advantage of giving a redundancy to the structure itself by using RF switches. The parastics of a power resistor, that would be a problem in design process, are removed by both slot lines and cavity resonators, and the comon node in the circuit is rdesigned as a planar topology, and thus a new type of 4-way radial power combiner/divider is accomplished at 1840 ~ 1870 MH PCS frequency band. The insertion loss, reflection, and isolation characteristics of 40way radial power combiner/divider which can be adaptable to PCS system in this thesis are -0.3dB, -24dB,a dn -27dB respectively.