• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.334-334
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• 2012

Transparent oxide semiconductors have recently attracted much attention as channel layer materials due to advantageous electrical and optical characteristics such as high mobility, high stability, and good transparency. In addition, transparent oxide semiconductor can be fabricated at low temperature with a low production cost and it permits highly uniform devices such as large area displays. A variety of thin film transistors (TFTs) have been studied including ZnO, InZnO, and InGaZnO as the channel layer. Recently, there are many studies for substitution of Ga in InGaZnO TFTs due to their problem, such as stability of devices. In this work, new quaternary compound materials, tantalum-indium-tin oxide (TaInSnO) thin films were fabricated by using co-sputtering and used for the active channel layer in thin film transistors (TFTs). We deposited TaInSnO films in a mixed gas (O2+Ar) atmosphere by co-sputtering from Ta and ITO targets, respectively. The electric characteristics of TaInSnO TFTs and thin films were investigated according to the RF power applied to the $Ta_2O_5$ target. The addition of Ta elements could suppress the formation of oxygen vacancies because of the stronger oxidation tendency of Ta relative to that of In or Sn. Therefore the free carrier density decreased with increasing RF power of $Ta_2O_5$ in TaInSnO thin film. The optimized characteristics of TaInSnO TFT showed an on/off current ratio of $1.4{\times}108$, a threshold voltage of 2.91 V, a field-effect mobility of 2.37 cm2/Vs, and a subthreshold swing of 0.48 V/dec.

• Journal of the Korean Ceramic Society
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• v.32 no.7
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• pp.761-768
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• 1995

Double layered BaTiO3 thin films with high dielectric constant as well as good insulating property were prepared for the application to low voltage driving thin film electroluminescent (TFEL) device. BaTiO3 thin films were formed by rf-magnetron sputtering technique. Amorphous and polycrystalline BaTiO3 thin films were deposited at the substrate temperatures of room temperature and 55$0^{\circ}C$, respectively. Two kinds of films prepared under these conditions showed high resistivity and high dielectric constant. The figure of merit (=$\varepsilon$r$\times$Eb.d) of polycrystalline BaTiO3 thin film was very high (8.43$\mu$C/$\textrm{cm}^2$). The polycrystalline BaTiO3 showed a substantial amount of leakage current (I), under the high electric field above 0.5 MV/cm. The double layered BaTiO3 thin film, i.e., amorphous BaTiO3 layer coated polycrystalline BaTiO3 thin film, was prepared by the new stacking method and showed very good dielectric and insulating properties. It showed a high dielectric constant fo 95 and leakage current density of 25 nA/$\textrm{cm}^2$ (0.3MV/cm) with the figure of merit of 20$\mu$C/$\textrm{cm}^2$. The leakage current density in the double layered BaTiO3 was much smaller than that in polycrystalline BaTiO3 under the high electric field. The saturated brightness of the devices using double layered BaTiO3 was about 220cd/$m^2$. Threshold voltage of TFEL devices fabricated on double layered BaTiO3 decreased by 50V compared to the EL devices fabricated on amorphous BaTiO3.

• Journal of IKEEE
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• v.4 no.2 s.7
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• pp.181-191
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• 2000

In this paper, two schemes of generating reference voltages using enhancement-mode MOS transistors and resistors are proposed. The first one is a voltage-mode scheme where the temperature compensation is made by summing a voltage component proportional to a threshold voltage and a voltage component proportional to a thermal voltage. In the second one, that is a current-mode scheme, the temperature compensation is made by summing a current component proportional to a threshold voltage and a current component proportional to a thermal voltage. The designed circuits have been simulated using a $0.65{\mu}m$ n-well CMOS process parameters. The voltage-mode circuit has a temperature coefficient less than $48.0ppm/^{\circ}C$ and a power-supply(VDD) coefficient less than 0.21%/V for a temperature range of $-30^{\circ}C{\sim}130^{\circ}C$ and a VDD range of $3V{\sim}12V$. The current-mode circuit has a temperature coefficient less than $38.2ppm/^{\circ}C$ and a VDD coefficient less than 0.8%/V for $-30^{\circ}C{\sim}130^{\circ}C\;and\; 4V{\sim}12V$. The power consumption of the voltage-mode and current-mode circuits are $27{\mu}W\;and\;65{\mu}W$ respectively for 5V and $30^{\circ}C$. Measurement results show that the voltage-mode reference circuit has a VDD coefficient less than 0.63%/V for $30^{\circ}C{\sim}100^{\circ}C$ and has a temperature coefficient less than $490ppm/^{\circ}C\;for\;3V{\sim}6V$. The proposed reference circuits are simple and thus easy to design. The proposed current-mode reference circuit can be designed to generate a wide range of reference voltages.

• Korean journal of applied entomology
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• v.35 no.2
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• pp.119-125
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• 1996

Temperature-dependent development study for overwintered eggs of Pseudococcus comstocki (Kuwana) wasconducted to develop a forecasting model for egg hatch date. Hatch times of overwintered eggs were comparedat five constant temperatures (10, 15, 20, 25, 27$^{\circ}$C) and different collection dates. A nonlinear, four-parameterdevelopmental model with high temperature inhibition accurately described (R2=0.9948) mean developmentalrates of all temperatures. Variation in developmental times was modeled(~~=0.972w9)it h a cumulative Weibullfunction. Least-squares linear regression (rate=O.O06358[Temp.]-0.07566)d escribed development in the linearregion (15-25$^{\circ}$C) of the development curve. The low development threshold temperature was estimated 11.9"Cand 154.14 degree-days were required for complete development. The linear degree-day model (thermal summation)and rate summation model (Wagner et al. 1985) were validated using field phenology data. In degreedaymodels, mean-minus-base method, sine wave method, and rectangle method were used in estimation of dailythermal units. Mean-minus-base method was 18 to 28d late, sine wave method was 11 to 14d late, rectanglemethod was 3 to 5d late, and rate summation model was 2 to 3d late in predicting 50% hatch of overwinteredeggs. hatch of overwintered eggs.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.137-137
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• 2009

Thin-film transistors (TFTs) that can be prepared at low temperatures have attracted much attention due to the great potential for flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited by low field effect mobility or rapidly degraded after exposing to air in many cases. Another approach is amorphous oxide semiconductors. Amorphous oxide semiconductors (AOSs) have exactly attracted considerable attention because AOSs were fabricated at room temperature and used lots of application such as flexible display, electronic paper, large solar cells. Among the various AOSs, a-IGZO was considerable material because it has high mobility and uniform surface and good transparent. The high mobility is attributed to the result of the overlap of spherical s-orbital of the heavy pest-transition metal cations. This study is demonstrated the effect of thickness channel layer from 30nm to 200nm. when the thickness was increased, turn on voltage and subthreshold swing were decreased. a-IGZO TFTs have used a shadow mask to deposit channel and source/drain(S/D). a-IGZO were deposited on SiO2 wafer by rf magnetron sputtering. using power is 150W, working pressure is 3m Torr, and an O2/Ar(2/28 SCCM) atmosphere at room temperature. The electrodes were formed with Electron-beam evaporated Ti(30nm) and Au(70nm) structure. Finally, Al(150nm) as a gate metal was evaporated. TFT devices were heat treated in a furnace at $250^{\circ}C$ in nitrogen atmosphere for an hour. The electrical properties of the TFTs were measured using a probe-station to measure I-V characteristic. TFT whose thickness was 150nm exhibits a good subthreshold swing(S) of 0.72 V/decade and high on-off ratio of 1E+08. Field effect mobility, saturation effect mobility, and threshold voltage were evaluated 7.2, 5.8, 8V respectively.

• Korean journal of applied entomology
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• v.51 no.4
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• pp.421-429
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• 2012

The developmental time period of Aphis gossypii was studied in laboratory (six constant temperatures from 15 to $30^{\circ}C$ with 50~60% RH, and a photoperiod of 14L:10D) and in a cucumber plastic house. The mortality of A. gossypii in the laboratory was high in the 2nd (20.0%) and 3rd stage(13.3%) at low temperature but high in the 3rd (26.7%) and 4th stage (33.3%) at high temperatures. Mortality in the plastic house was high in the 1st and 2nd stage but there was no mortality in the 4th stage at low temperature. The total developmental period was longest at $15^{\circ}C$ (12.2 days) in the laboratory and shortest at $28.5^{\circ}C$ (4.09 days) in the plastic house. The lower threshold temperature at the total nymphal stage was $6.8^{\circ}C$ in laboratory. The thermal constant required to reach the total nymphal stage was 111.1DD. The relationship between the developmental rate and temperature fit the nonlinear model of Logan-6 which has the lowest value for the Akaike information criterion(AIC) and Bayesian information criterion(BIC). The distribution of completion of each development stage was well described by the 3-parameter Weibull function ($r^2=0.89{\sim}0.96$). This model accurately described the predicted and observed outcomes. Thus it is considered that the model can be used for predicting the optimal spray time for Aphis gossypii.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.105-110
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• 2008

We have proposed a new structure of poly-silicon thin film transistor(TFT) which was fabricated the LDD region using doping oxide with graded spacer by etching shape retio. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $HT_2$/plasma processes are fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring /analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si Brain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplity of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of Plant Biotechnology
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• v.35 no.4
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• pp.281-290
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• 2008

In plant, Receptor-like kinases (RLKs) are protein family, though its function is not yet understood, consisted of a predicted signal sequence, single transmembrane region, and cytoplasmic kinase domain. RLKs are involved in hormonal response pathways, cell differentiation, plant growth and development, self-incompatibility, and symbiont and pathogen recognition. In this study, expression levels of RLG1, RLG5, RLG6, RLG#6, RLG8, RLG10, RLG17, RLG18 and RLG20 were analyzed by Real-time PCR, when rice (Oryzae sativa) was treated abiotic stress. The expression levels of all RLGs were compared each other by analyzed value of threshold cycles ($C_T$). Consequently, RLGs were suppressed by NaCl as salinity stress, and expression of each RLK genes were showed difference treated salicylic acid and wound, respectively. However, All RLGs were induced under low temperature condition. Therefore, our results indicate protection-function of RLK genes to be an early response of rice against cold weather.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.53.2-53.2
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• 2010

지금까지 능동 구동 디스플레이의 TFT backplane에 사용하고 있는 채널 물질로는 수소화된 비정질 실리콘(a-Si:H)과 저온 폴리실리콘(low temperature poly-Si)이 대표적이다. 수소화된 비정질 실리콘은 TFT-LCD 제조에 주로 사용되는 물질로 제조 공정이 비교적 간단하고 안정적이며, 생산 비용이 낮고, 소자 간 특성이 균일하여 대면적 디스플레이 제조에 유리하다. 그러나 a-Si:H TFT의 이동도(mobility)가 1 cm2/Vs이하로 낮아 Full HD 이상의 대화면, 고해상도, 고속 동작을 요구하는 UD(ultra definition)급 디스플레이를 개발하는데 있어 한계 상황에 다다르고 있다. 또한 광 누설 전류(photo leakage current)의 발생을 억제하기 위해서 화소의 개구율(aperture ratio)을 감소시켜야하므로 패널의 투과율이 저하되고, 게이트 전극에 지속적으로 바이어스를 인가 시 TFT의 문턱전압(threshold voltage)이 열화되는 문제점을 가지고 있다. 문제점을 극복하기 위한 대안으로 근래 투명 산화물 반도체(transparent oxide semiconductor)가 많은 관심을 얻고 있다. 투명 산화물 반도체는 3 eV 이상의 높은 밴드갭(band-gap)을 가지고 있어 광 흡수도가 낮아 투명하고, 광 누설 전류의 영향이 작아 화소 설계시 유리하다. 최근 다양한 조성의 산화물 반도체들이 TFT 채널 층으로의 적용을 목적으로 활발하게 연구되고 있으며 ZnO, SnO2, In2O3, IGO(indium-gallium oxide), a-ZTO(amorphous zinc-tin-oxide), a-IZO (amorphous indium-zinc oxide), a-IGZO(amorphous indium-galliumzinc oxide) 등이 그 예이다. 이들은 상온 또는 $200^{\circ}C$ 이하의 낮은 온도에서 PLD(pulsed laser deposition)나 스퍼터링(sputtering)과 같은 물리적 기상 증착법(physical vapor deposition)으로 손쉽게 증착이 가능하다. 특히 이중에서도 a-IGZO는 비정질임에도 불구하고 이동도가 $10\;cm2/V{\cdot}s$ 정도로 a-Si:H에 비해 월등히 높은 이동도를 나타낸다. 이와 같이 a-IGZO는 비정질이 가지는 균일한 특성과 양호한 이동도로 인하여 대화면, 고속, 고화질의 평판 디스플레이용 TFT 제작에 적합하고, 뿐만 아니라 공정 온도가 낮은 장점으로 인해 플렉시블 디스플레이(flexible display)의 backplane 소재로서도 연구되고 있다. 본 실험에서는 rf sputtering을 이용하여 증착한 a-IGZO 박막에 대하여 열처리 조건 변화에 따른 a-IGZO 박막들의 광학적, 전기적 특성변화를 살펴보았고, 이와 더불어 a-IGZO 박막을 TFT에 적용하여 소자의 특성을 분석함으로써, 열처리에 따른 Transfer Curve에서의 우리가 요구하는 Threshold Voltage(Vth)의 변화를 관찰하였다.