• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.455-456
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• 2008

New CMOS ROM cell is reported in this paper, distinguished from conventional ones in that it can be re-programmed by multi-times. It uses the comparator offset as the physical storage quantity and the MOSFET FN stress effect for offset programming. It demands very low offset for read, and works well in very low voltage. It can become a promising ROM solution for various SoC systems.

• 조명전기설비학회논문지
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• 제27권2호
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• pp.22-28
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• 2013

In this paper, the low cost SOA Dimming Driver which consisted of LabVIEW programming part capable of current pattern design, DAQ module for analog voltage output, and voltage to current converter has realized. The output current(possible to 3A) from the Driver was clearly constant without ripple and also showed no variance until 1mA unit for a long time operation. The proposed low cost Driver can replace the previous high cost SOA Drivers for wavelength swept lasers fully and provide the convenience and safety of auto-supplying a designed current pattern.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• 대한전기학회논문지:전력기술부문A
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• 제54권9호
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• pp.434-440
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• 2005

This paper describes an optimized Scheme of reactive-power compensation for the low short-circuit-ratio AC system interconnected with the HVDC system. An HVDC system interconnected with tile low SCR AC system is vulnerable to the ac voltage variation, which brings about the commutation failure of the converter. This problem can be solved using optimized compensation of reactive power. In this study, a benchmark system for HVDC system interconnected with low SCR AC system is derived using PSS/E simulation. Then an optimized srheme for reactive power compensation was derived using integer programming. The feasibility of proposed scheme was analyzed through silnulations with PSS/E and PSCAD/EMTDC. The proposed scheme can compensate the reactive power accurately and minimize the number of switching for harmonic filters and shunt reactors.

• 한국정보통신학회논문지
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• 제14권8호
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• pp.1877-1886
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• 2010

본 논문에서는 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로를 설계하였다. 공급전원이 낮아지더라도 외부 프로그램 전원을 사용하여 높은 프로그램 파워를 eFuse (electrical fuse)에 공급하면서 셀의 읽기 전류를 줄일 수 있는 듀얼 포트 eFuse 셀을 제안하였다. 그리고 제안된 듀얼 포트 eFuse 셀은 파워-온 읽기 기능으로 eFuse의 프로그램 정보가 D-래치에 자동적으로 저장되도록 설계하였다. 또한 메모리 리페어 주소와 메모리 액세스 주소를 비교하는 주소 비교 회로는 dynamic pseudo NMOS 로직으로 구현하여 기존의 CMOS 로직을 이용한 경우 보다 레이아웃 면적을 19% 정도 줄였다. 전기적인 퓨즈 프로그래밍을 이용한 1T-SRAM 리페어용 리던던시 제어 회로는 동부하이텍 $0.11{\mu}m$ Mixed Signal 공정을 이용하여 설계되었으며, 레이아웃 면적은 $249.02{\times}225.04{\mu}m^{2}$이다.

• 한국진공학회지
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• 제9권3호
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• pp.263-266
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• 2000

본 논문에서는 낮은 구동 전압에서 동작하고 안정된 on/off 상태를 갖는 Al/$TiO_2-SiO_2$/Mo 형태의 안티퓨즈를 제작하였다. 하부전극으로 사용된 Mo 금속은 표면상태가 부드럽고 녹는점이 높은 매우 안정된 금속으로, 표면 위에 제조된 $SiO_2$ 특성을 매우 안정되게 유지시켰다. 또한 $TiO_2$절연막을 $SiO_2$절연막 위에 복층 구조로 증착하여, Ti 금속의 침투로 인한 $SiO_2$ 절연막의 약화로 동일 두께(100 $\AA$)의 $SiO_2$, 단일막에 비하여 향상된 절연파괴 전압을 얻을 수 있었다. $TiO_2-SiO_2$ 이중절연막을 사용하여 적정 절연파괴전압 및 ON-저항을 구현하였으며, 두께가 두꺼워짐으로 인해 바닥금속의 거칠기의 영향을 최소화시킬 수 있었다. 이중 절연막의 두께는 250 $\AA$이고 프로그래밍 전압은 9.0 V이고 약 65 $\Omega$의 on 저항을 얻을 수 있었다.

• 한국전기전자재료학회논문지
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• 제19권10호
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• pp.918-922
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• 2006

Chalcogenide Phase change memory has the high performance necessary for next-generation memory, because it is a nonvolatile memory with high programming speed, low programming voltage, high sensing margin, low power consumption and long cycle duration. To minimize the power consumption and the program voltage, the new composition material which shows the better phase-change properties than conventional $Ge_2Sb_2Te_5$ device has to be needed by accurate material engineering. In the present work, we investigate the basic thermal and the electrical properties due to phase-change compared with chalcogenide-based new composition $Ge_1Se_1Te_2$ material thin film and convetional $Ge_2Sb_2Te_5$ PRAM thin film. The fabricated new composition $Ge_1Se_1Te_2$ thin film exhibited a successful switching between an amorphous and a crystalline phase by applying a 950 ns -6.2 V set pulse and a 90 ns -8.2 V reset pulse. It is expected that the new composition $Ge_1Se_1Te_2$ material thin film device will be possible to applicable to overcome the Set/Reset problem for the nonvolatile memory device element of PRAM instead of conventional $Ge_2Sb_2Te_5$ device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.258-258
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• 2010

In this work, back bias effects in the program of the silicon-oxide-nitride-oxide-silicon (SONOS) cell using two-step pulse sequence, are investigated. Two-step pulse sequence is composed of the forward biases for collecting the electrons at the substrate terminal and back bias for injecting the hot electrons into the nitride layer. With an aid of the back bias for electron injection, we obtain a program time as short as 600 ns and an ultra low-voltage operation with a substrate voltage of -3 V.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.254.2-254.2
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• 2014

The Transmission Fourier Transform Infrared spectroscopy (FTIR) of SiOx charge storage layer with the richest silicon content showed an assignment at peaks around 2000~2300 cm-1. It indicated that the existence of many silicon phases and defect sources in the matrix of the SiOx films. The total hysteresis width is the sum of the flat band voltage shift (${\Delta}VFB$) due to electron and hole charging. At the range voltage sweep of ${\pm}15V$, the ${\Delta}VFB$ values increase of 0.57 V, 1.71 V, and 13.56 V with 1/2, 2/1, and 6/1 samples, respectively. When we increase the gas ratio of SiH4/N2O, a lot of defects appeared in charge storage layer, more electrons and holes are charged and the memory window also increases. The best retention are obtained at sample with the ratio SiH4/N2O=6/1 with 82.31% (3.49V) after 103s and 70.75% after 10 years. The high charge storage in 6/1 device could arise from the large amount of silicon phases and defect sources in the storage material with SiOx material. Therefore, in the programming/erasing (P/E) process, the Si-rich SiOx charge-trapping layer with SiH4/N2O gas flow ratio=6/1 easily grasps electrons and holds them, and hence, increases the P/E speed and the memory window. This is very useful for a trapping layer, especially in the low-voltage operation of non-volatile memory devices.

• 센서학회지
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• 제8권2호
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• pp.163-170
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• 1999

각각 8개의 N과 P채널 EEPROM을 이용하여 광섬유 엔진 모니터용 압력센서를 위한 A/D 변환기를 설계하였다. EEPROM의 쓰기와 소거동작에서 요구되는 높은 프로그래밍 전압의 크기를 낮추기 위한 지역전계강화 효과가 소개된다. 프로그래밍 모드에서 EEPROM의 선형적 저장능력을 관찰하기 위해 MOSIS의 $1.2\;{\mu}m$ double-poly CMOS 공정을 이용하여 셀이 제작되었다. 그 결과 1.25V와 2V구간에서 10mV 미만의 오차 내에서 셀이 선형적으로 프로그램 되는 것을 보았다. 이러한 실험 결과를 이용하여 프로그램 가능한 A/B 변환기의 동작이 Hspice에서 시뮤레이션 되었으며, 그 결과 A/D 변환기가 $37\;{\mu}W$의 전력을 소모하고 동작주파수는 333MHz 정도인 것으로 관찰되었다.