• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.451-454
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• 2003

In this paper, the research trend and the sate-of-the-art of low cost motor drives are introduced with the recently increasing interest In various industrial applications, such as home appliance, hybrid electric vehicles, wind power systems, fuel cell systems, and etc. Based on this presented work, it is highly expected the power electronics technologies, which are accumulated through the last 20 years, can be effectively applied to actual application fields.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• Electronics and Telecommunications Trends
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• v.36 no.5
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• pp.92-102
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• 2021

Owing to various restrictions in-field application, the low-speed, low-power-based industrial Internet-of-Things (IoT) network built in extremely harsh industrial environment sites requires multi-hop, channel hopping, and low-latency transmission characteristics. In the past, wired networks were used in industrial facilities; however, network technologies based on the Industrial IoT Network standard standardized for industrial applications, such as WirelessIO link, WirelessHART, SmartMesh, and eStar Link satisfy industrial requirements. Recently, the use of industrial IoT networks in industrial facilities has rapidly expanded. This paper covers the developments in industrial IoT network technologies and summarizes the major industrial IoT standard technologies that meets the requirements of industrial sites.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.855-859
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• 2004

The Japanese National Project "Carbon Nanotube FED" is developing a high image-quality and low power-consumption field emission display (FED) by applying carbon nanotube (CNT) to the electron source. A uniform electron source with a flat-film CNTs and fine structure triodes Fir suppressing the deviation of emission is required. For realizing an FED panel, it is also necessary to develop the glass-bulb technologies for vacuum sealing, and display technologies for driving the panel by circuit electronic and for evaluating the picture quality by measuring. By achieving these technologies, an FED compatible with conventional Cathode Ray Tubes (CRTs) will be realized.

• IEMEK Journal of Embedded Systems and Applications
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• v.13 no.3
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• pp.133-141
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• 2018

There are increasing interests on smart home systems. However, most of the existing works focus on the functionality itself. In this paper, we propose an extensible smart home system based on low power networking such as CoAP, 6LoWPAN, and Zigbee. The proposed home IoT system consists of Home APP, Home Server, Home Broker, and Power Devices. Each component of the system is connected by the low-power network technologies aforementioned. As the end device, Power Device senses the current consumption of the attached appliance and controls the power to it. Power Device reports the sensing data to Home Server via Home Broker. The Home Broker enhances the scalability of the system. Home Broker extends the service area and the user's services, and it manages the connection of the underlying devices and processes, and transmits data to Home Server from Power Devices. Through the experimental evaluation, we show that the proposed system achieves the design goals such as extensibility and low power networking.

• International Journal of Internet, Broadcasting and Communication
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• v.12 no.1
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• pp.90-94
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• 2020

Artificial intelligence (AI) is software that learns large amounts of data and provides the desired results for certain patterns. In other words, learning a large amount of data is very important, and the role of memory in terms of computing systems is important. Massive data means wider bandwidth, and the design of the memory system that can provide it becomes even more important. Providing wide bandwidth in AI systems is also related to power consumption. AlphaGo, for example, consumes 170 kW of power using 1202 CPUs and 176 GPUs. Since more than 50% of the consumption of memory is usually used by system chips, a lot of investment is being made in memory technology for AI chips. MRAM, PRAM, ReRAM and Hybrid RAM are mainly studied. This study presents various memory technologies that are being studied in artificial intelligence chip design. Especially, MRAM and PRAM are commerciallized for the next generation memory. They have two significant advantages that are ultra low power consumption and nearly zero leakage power. This paper describes a comparative analysis of the four representative new memory technologies.

• KIEE International Transactions on Power Engineering
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• v.3A no.3
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• pp.168-176
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• 2003

The Korea Electric Power Corporation (KEPCO) has installed an 80 MY A Unified Power Flow Controller (UPFC) at its 154㎸ 'Kang-Jin Substation in South Korea. The device, manufactured by Siemens & Hyusung, has been operational since October 2002. The Korea Electric Power Research Institute (KEPRI), a division of KEPCO was tasked to study operational strategies that could be employed for the UPFC and surrounding reactive support devices concerning problems of low voltages and overloads in the Mokpo & Gwangju areas. Particular apprehension surrounded the possibility of delay in the installation of a new 345㎸ transmission line from 2005 to beyond 2010. The studies were to specifically determine whether these problems could be eliminated by application of a UPFC. The analysis included determining the UPFC operating point under various conditions, investigations of the coordination between the UPFC and a HYDC line terminating in this area, and the design of a supplementary damping controller for the UFPC. This paper summarizes the results of those studies, demonstrating the dynamic characteristics of the operation of this UPFC operation in the Korean power system.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.253-256
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• 2000

This paper describes a DSP implementation of a real-time 3D sound localization algorithm with the use of a low power embedded DSP. A distinctive feature of this implementation is that the audible frequency band is divided into three, in accordance with the sound reflection and diffraction phenomena through different media from a certain sound source to human ears, and then in each subband a specific implementation procedure of the 3D sound localization is devised so as to operate real-time at a low frequency of 50MHz on a 16bit fixed-point DSP. Thus out DSP implementation can provide a listener with 3D sound effects through a headphone at low cost and low power consumption.

• ETRI Journal
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• v.37 no.1
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• pp.107-117
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• 2015

This paper presents an energy-efficient (low power) prime-field hyperelliptic curve cryptography (HECC) processor with uniform power draw. The HECC processor performs divisor scalar multiplication on the Jacobian of genus 2 hyperelliptic curves defined over prime fields for arbitrary field and curve parameters. It supports the most frequent case of divisor doubling and addition. The optimized implementation, which is synthesized in a $0.13{\mu}m$ standard CMOS technology, performs an 81-bit divisor multiplication in 503 ms consuming only $6.55{\mu}J$ of energy (average power consumption is $12.76{\mu}W$). In addition, we present a technique to make the power consumption of the HECC processor more uniform and lower the peaks of its power consumption.

• Journal of IKEEE
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• v.17 no.3
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• pp.365-370
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• 2013

Power MOSFET is developed in power savings, high efficiency, small size, high reliability, fast switching, and low noise. Power MOSFET can be used in high-speed switching transistors devices. Recently attention given to the motor and the application of various technologies. Power MOSFET is a voltage-driven approach switching device and designed to handle on large power, power supplies, converters, motor controllers. In this paper, the 400 V Planar type, and the trench type for realization of low on-resistance are designed. Trench Gate Power MOSFET Vth : 3.25 V BV : 484 V Ron : 0.0395 Ohm has been optimized.