• Title/Summary/Keyword: Low power systems

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Low-Power Cache Design by using Locality Buffer and Address Compression (지역 버퍼와 주소 압축을 통한 저전력 캐시 설계)

  • Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.9
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    • pp.11-19
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    • 2013
  • Most modern computer systems employ cache systems in order to alleviate the access time gap between processor and memory system. The power dissipated by the cache systems becomes a significant part of the total power dissipated by whole microprocessor chip. Therefore, power reduction in the cache system becomes one of the important issues. Partial tag cache is the system for the least power consumption. The main power reduction for this method is due to the use of small partial tag matching, not full tag matching. In this paper, we first analyze the previous regular partial tag cache systems and propose a new address matching mechanism by using locality buffer and address compression. In simulation results, the proposed model shows 18% power reduction in average, still providing same performance level, compared to regular cache.

Design of the low noise CMOS LDO regulator for a low power capacitivesensor interface (저전력 용량성 센서 인터페이스를 위한 저잡음 CMOS LDO 레귤레이터 설계)

  • Kwon, Bo-Min;Jung, Jin-Woo;Kim, Ji-Man;Park, Yong-Su;Song, Han-Jung
    • Journal of Sensor Science and Technology
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    • v.19 no.1
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    • pp.25-30
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    • 2010
  • This paper presents a low noise CMOS regulator for a low power capacitive sensor interface in a $0.5{\mu}m$ CMOS standard technology. Proposed LDO regulator circuit consist of a voltage reference block, an error amplifier and a new buffer between error amplifier and pass transistor for a good output stability. Conventional source follower buffer structure is simple, but has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide band OTA instead of source follower structure for a buffer. From SPICE simulation results, we got 0.8 % line regulation and 0.18 % load regulation.

Comparative Study on 220V AC Feed System and 300V DC Feed System for Internet Data Centers

  • Kim, Hyo-Sung
    • Journal of Power Electronics
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    • v.12 no.1
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    • pp.157-163
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    • 2012
  • Internet Data Centers (IDCs), which are essential facilities in the modern IT industry, typically have scores of MW of concentrated electric loads. The provision of an Uninterruptible Power Supply (UPS) is necessary for the power feed system of IDCs owing to the need for stable power. Thus, conventional IDC AC power feed systems have three cascaded power conversion stages, (AC-DC), (DC-AC), and (AC-DC), resulting in a very low conversion efficiency. In comparison, DC power feed systems require only a single power conversion stage (AC-DC) to supply AC main power to DC server loads, resulting in comparatively high conversion efficiency and reliability [4-11]. This paper compares the efficiencies of a 220V AC power feed system with those of a 300V DC power feed system under equal load conditions, as established by the Mok-Dong IDC of Korea Telecom Co. Ltd. (KT). Experimental results show that the total operation efficiency of the 300V DC power feed system is approximately 15% higher than that of the 220V AC power feed system.

WiSeMote: a novel high fidelity wireless sensor network for structural health monitoring

  • Hoover, Davis P.;Bilbao, Argenis;Rice, Jennifer A.
    • Smart Structures and Systems
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    • v.10 no.3
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    • pp.271-298
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    • 2012
  • Researchers have made significant progress in recent years towards realizing effective structural health monitoring (SHM) utilizing wireless smart sensor networks (WSSNs). These efforts have focused on improving the performance and robustness of such networks to achieve high quality data acquisition and distributed, in-network processing. One of the primary challenges still facing the use of smart sensors for long-term monitoring deployments is their limited power resources. Periodically accessing the sensor nodes to change batteries is not feasible or economical in many deployment cases. While energy harvesting techniques show promise for prolonging unattended network life, low power design and operation are still critically important. This research presents the WiSeMote: a new, fully integrated ultra-low power wireless smart sensor node and a flexible base station, both designed for long-term SHM deployments. The power consumption of the sensor nodes and base station has been minimized through careful hardware selection and the implementation of power-aware network software, without sacrificing flexibility and functionality.

Obstacle Avoidance Algorithm of Hybrid Wheeled and Legged Mobile Robot Based on Low-Power Walking (복합 바퀴-다리 이동형 로봇의 저전력 보행 기반 장애물 회피 알고리즘)

  • Jeong, Dong-Hyuk;Lee, Bo-Hoon;Kim, Yong-Tae
    • Journal of the Korean Institute of Intelligent Systems
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    • v.22 no.4
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    • pp.448-453
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    • 2012
  • There are many researches to develop robots that improve its mobility to adapt in various uneven environments. In the paper, a hybrid wheeled and legged mobile robot is designed and a obstacle avoidance algorithm is proposed based on low power walking using LRF(Laser Range Finder). In order to stabilize the robot's motion and reduce energy consumption, we implement a low-power walking algorithm through comparison of the current value of each motors and correction of posture balance. A low-power obstacle avoidance algorithm is proposed by using LRF sensor. We improve walking stability by distributing power consumption and reduce energy consumption by selecting a shortest navigation path of the robot. The proposed methods are verified through walking and navigation experiments with the developed hybrid robot.

Combined Design of PSS and STATCOM Controllers for Power System Stability Enhancement

  • Rohani, Ahmad;Tirtashi, M. Reza Safari;Noroozian, Reza
    • Journal of Power Electronics
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    • v.11 no.5
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    • pp.734-742
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    • 2011
  • In this paper a robust method is presented for the combined design of STATCOM and Power System Stabilizer (PSS) controllers in order to enhance the damping of the low frequency oscillations in power systems. The combined design problems among PSS and STATCOM internal ac and dc voltage controllers has been taken into consideration. The equations that describe the proposed system have been linearized and a Fuzzy Logic Controller (FLC) has been designed for the PSS. Then, the Particle Swarm Optimization technique (PSO) which has a strong ability to find the most optimistic results is employed to search for the optimal STATCOM controller parameters. The proposed controllers are evaluated on a single machine infinite bus power system with the STATCOM installed in the midpoint of the transmission line. The results analysis reveals that the combined design has an excellent capability in damping a power system's low frequency oscillations, and that it greatly enhances the dynamic stability of power systems. Moreover, a system performance analysis under different operating conditions and some performance indices studies show the effectiveness of the combined design.

Voltage Source Resonant Inverter for Excimer Gas Discharge Load

  • Koudriavtsev, Oleg;Nakaoka, Mutsuo
    • Journal of Power Electronics
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    • v.2 no.3
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    • pp.206-211
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    • 2002
  • Silent gas discharge method has been widely applied fur ozone production, ultraviolet light and UV laser generation. Since ozone and ultraviolet applications have tendency to spread widely in industry, the development of efficient and low - cost power supply for such systems is an important task at present. This paper introduces high-frequency inverter type mode power supply designed fur ozone generation tube and ultraviolet generation excimer lamp and considerations on the design of the inverter and pulse density modulation control strategy applied in it.

Asynchronous Circuit Design Combined with Power Switch Structure (파워 스위치 구조를 결합한 비동기 회로 설계)

  • Kim, Kyung Ki
    • Journal of Korea Society of Industrial Information Systems
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    • v.21 no.1
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    • pp.17-25
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    • 2016
  • This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a $4{\times}4$ multiplier designed using 0.11 um CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

Optimal Design Considerations of a Bus Converter for On-Board Distributed Power Systems

  • Abe, Seiya;Hirokawa, Masahiko;Shoyama, Masahito;Ninomiya, Tamotsu
    • Journal of Power Electronics
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    • v.9 no.3
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    • pp.447-455
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    • 2009
  • The power supply systems, which require low-voltage / high-current output has been changing from the conventional centralized power system to a distributed power system. The distributed power system consists of a bus converter and POL. The most important factor is the system stability in bus architecture design. The overlap between the output impedance of a bus converter input impedance of POL causes system instability and has been an actual problem. By increasing the bus capacitor, the system stability can be easily improved. However, due to limited space on the system board, the increasing of bus capacitors is impractical. An urgent solution of this issue is strongly desired. This paper presents the output impedance design for on-board distributed power system by means of three control schemes of a bus converter. The output impedance peak of the bus converter and the input impedance of the POL are analyzed and then conformed experimentally for stability criterion. Furthermore, the design process of each control schemes for system stability is proposed.

Low-power memory based FFT structure for high speed UWB (UWB용 저전력 Memory based FFT 구조)

  • Choi, Dong-Kyu;Jang, Young-Beom
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.215-216
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    • 2008
  • Ultra wideband (UWB) system is one of the promising solutions for future short-range communication which has recently received a great attention by many researchers. In this paper, we proposed 128-point low power FFT structure based on the memory for UWB systems. The proposed structure can improve implementation area and power consumption efficiency as it consists of one of the butterfly PE and a little memory.

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