• Analytical Science and Technology
• /
• v.7 no.3
• /
• pp.253-260
• /
• 1994

Analytical characteristics of low power-low flow inductively coupled plasma-atomic emission spectometry(ICP-AES) has been studied. Although the net intensity of the low power ICP is lower than the moderate power ICP, the signal to background ratio becomes higher since the background intensity decreases with decreasing the RF power. The detection limit of the low power ICP is comparable with that of the moderate power ICP. The dynamic range of the calibration curve of the low power ICP is $10^4{\sim}10^5$. The ionization interferences by alkali metals increase with increasing the carrier gas flow rate, but the effects are not varied significantly with the RF power.

• ETRI Journal
• /
• v.33 no.4
• /
• pp.611-620
• /
• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.22 no.1
• /
• pp.1-6
• /
• 2022

In this paper, the design of lightweight S-Box structure for implementing a low power AES cryptosystem based on composite field. In this approach, the S-Box is designed as a simple structure by which the three modules of x², λ, and GF((2²)²) merge into one module for improving the usable area and processing speed on GF(((2²)²)²). The designed AES S-Box is modelled in Veilog-HDL at structural level, and a logic synthesis is also performed through the use of Xilinx ISE 14.7 tool, where Spartan 3s1500l is used as a target FPGA device. It is shown that the designed S-Box is correctly operated through simulation result, where ModelSim 10.3. is used for performing timing simulation.

• Journal of Electrical Engineering and Technology
• /
• v.6 no.3
• /
• pp.418-422
• /
• 2011

For low-power sensor networks, a compact design of advanced encryption standard (AES) algorithm is needed. A very small AES core for ZigBee devices that accelerates computation in AES algorithms is proposed in this paper. The proposed AES core requires only one S-Box, which plays a major role in the optimization. It consumes less power than other block-wide and folded architectures because it uses fewer logic gates. The results show that the proposed design significantly decreases power dissipation; however, the resulting increased clock cycles for 128-bit block data processing are reasonable for IEEE 802.15.4 standard throughputs.

• Journal of IKEEE
• /
• v.19 no.1
• /
• pp.45-51
• /
• 2015

Recently, as WPAN (Wireless Personal Area Network) becomes the necessary feature in IoT (Internet of Things) devices, the importance of data security also hugely increases. In this paper, we present the low-complexity 128-bit AES-$CCM^*$ hardware IP for IEEE 802.15.4 standard. For low-cost and low-power implementation which is essentially required in IoT devices, we propose two optimization methods. First, the folded AES(Advanced Encryption Standard) processing core with 8-bit datapath is presented where composite field arithmetic is adopted for reduced hardware complexity. In addition, to support $CCM^*$ mode defined in IEEE 802.15.4, we propose the mode-toggling architecture which requires less hardware resources and processing time. With the proposed methods, the gate count of the proposed AES-$CCM^*$ IP can be lowered up to 57% compared to the conventional architecture.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.60 no.4
• /
• pp.262-266
• /
• 2011

In high data-rate communication systems, encryption/decryption must be processed in high speed. In this paper, we implement CCM security mode which is the basis of security. Specifically, we combine CCM with AES block encryption algorithm in hardware. With the combination, we can carry out encryption/decryption as well as data transmission/reception simultaneously without reducing data-rate, and we keep low-power consumption with high speed by optimizing CCM block.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.9 no.1
• /
• pp.296-308
• /
• 2015

Advanced Encryption Standard (AES) is widely used for protecting wireless sensor network (WSN). At the Workshop on Cryptographic Hardware and Embedded Systems (CHES) 2012, G$\acute{e}$rard et al. proposed an optimized collision attack and break a practical implementation of AES. However, the attack needs at least 256 averaged power traces and has a high computational complexity because of its byte wise operation. In this paper, we propose a novel double sieve collision attack based on bitwise collision detection, and an improved version with an error-tolerant mechanism. Practical attacks are successfully conducted on a software implementation of AES in a low-power chip which can be used in wireless sensor node. Simulation results show that our attack needs 90% less time than the work published by G$\acute{e}$rard et al. to reach a success rate of 0.9.

• KIISE Transactions on Computing Practices
• /
• v.22 no.7
• /
• pp.303-309
• /
• 2016

Recently, an increasing number of embedded processors such as ARM Mali begin to support GPGPU programming frameworks, such as OpenCL. Thus, GPGPU technologies that have been used in PC and server environments are beginning to be applied to the embedded systems. However, many embedded systems have different architectural characteristics compare to traditional PCs and low-power consumption and real-time performance are also important performance metrics in these systems. In this paper, we implement a parallel AES cryptographic algorithm for a modern embedded GPU using OpenCL, a standard parallel computing framework, and compare performance against various baselines. Experimental results show that the parallel GPU AES implementation can reduce the response time by about 1/150 and the energy consumption by approximately 1/290 compare to OpenMP implementation when 1000KB input data is applied. Furthermore, an additional 100 % performance improvement of the parallel AES algorithm was achieved by exploiting the characteristics of embedded GPUs such as removing copying data between GPU and host memory. Our results also demonstrate that higher performance improvement can be achieved with larger size of input data.

• Journal of the Semiconductor & Display Technology
• /
• v.3 no.2
• /
• pp.17-21
• /
• 2004

Aluminum nitride(AlN) thin films were deposited on silicon substrate by reactive RF magnetron sputtering without substrate heating. We investigated the dependence of some properties for AlN thin film on sputtering conditions such as working pressure, $N_2$ concentration and RF power. XRD, Ellipsometer and AES has been measured to find out structural properties and preferred orientation of AlN thin films. Deposition rate of AlN thin film was increased with an increase of RF power and decreased with an increase of $N_2$ concentration. AES in-depth measurements showed that stoichiometry of Aluminium and Nitrogen elements were not affected by $N_2$ concentration. It has shown that low working pressure, low $N_2$ concentration and high RF power should be maintained to deposit AlN thin film with a high degree of (0002) preferred orientation.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.77-86
• /
• 2010

This paper presents an efficient secure scan design technique which is based on a fake key and IEEE 1149.1 instruction to protect secret key from scan-based side channel attack for an Advanced Encryption Standard (AES) core embedded on an System-on-a-Chip (SoC). Our proposed secure scan design technique can be applied to crypto IP core which is optimized for applications without the IP core modification. The IEEE 1149.1 standard is kept, and low area, low power consumption, very robust secret-key protection and high fault coverage can be achieved compared to the existing methods.