• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.163-165
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• 2003

Over the past several years, the application extent of the real-time systems is being expanded with the progress of civilization. An effort to minimize power consumption at the system is being accomplished in several fields from the design of an analog/digital circuit up to the device level Things of this effort have included the power optimum-technique to minimize power consumption at the digital logic circuit and the dynamic managed skill by means o( the decision of the operating system. In this paper, we designed of low power system by using Power-optimized method. As an effective low-power design, we designed the low power system which it has a monitoring system within the main board and a personal computer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• 대한전자공학회논문지SD
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• 제48권10호
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• pp.33-38
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• 2011

본 논문에서는 로컬에서의 동기화를 위한 새로운 저 전력 동기화 기술을 제안하였다. 본 논문에서 제안하고 있는 저 전력 동기화 기술은 현재 널리 이용되고 있는 소스 동기화 방법과 비교하여 클록을 전송하는 대신 인에이블 신호를 전송하여 동기화를 함으로써 소스 동기화 방법의 장점과 데이터 전송속도는 그대로 유지하면서 동기화를 위한 회로와 배선에서 소모되는 전력을 50%이상 감소시킨다.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.1054-1057
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• 1993

A direct method of fuzzy inference and a fuzzy algorithm with learning function are applied to the steam generator level control of nuclear power plant. The fuzzy controller by use of direct inference can control the steam generator in the entire range of power level. There is a little long response time of fuzzy direct inference controller at low power level. The rule base of fuzzy controller with learning function is divided into two parts. One part of the rule base is provided to level control of steam generator at low power level (0%∼30% of full power). Response time of steam generator level control at low power level with this rule base is shown generator level control at low power level with this rule base is shown to be shorter than that of fuzzy controller with direct inference.

• 전기학회논문지P
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• 제62권3호
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• pp.145-150
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• 2013

A novel AC to DC PWM converters with unity input power factor are proposed to overcome the above shortcoming. The main function of these converters is to shape the input line current to force it exactly in phase with the input AC voltage. Therefore, the input power factor can be improved to near unity and the input current harmonics can be eliminated. In this paper, half-bridge converter with two active switches and two diodes are utilized for low-cost type UPS configuration. By having only two semiconductors in the current path at any time, losses can be reduced over the conventional boost topology. Also, this converter provides controllable dc-link voltage, high power factor, and low cost type converter by simple power circuits. Simulation results show that the proposed half-bridge converter/inverter control technique can be applied to single-phase low-cost type UPS systems successfully.

• Nuclear Engineering and Technology
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• 제48권1호
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• pp.211-217
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• 2016

Most nuclear power plants now utilize solid grounded low voltage systems. For safety and reliability reasons, the low voltage (LV) high resistance grounding (HRG) system is also increasingly used in the pulp and paper, petroleum and chemical, and semiconductor industries. Fault detection is easiest and fastest with a solidly grounded system. However, a solidly grounded system has many limitations such as severe fault damage, poor reliability on essential circuits, and electrical noise caused by the high magnitude of ground fault currents. This paper will briefly address the strengths and weaknesses of LV grounding systems. An example of a low voltage HRG system in the LV system of a nuclear power plant will be presented. The HRG system is highly recommended for LV systems of nuclear power plants if sufficient considerations are provided to prevent nuisance tripping of ground fault relays and to avoid the deterioration of system reliability.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• 한국산업융합학회 논문집
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• 제24권4_1호
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• pp.387-395
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• 2021

Distributed resources such as renewable energy sources and ESS are connected to the low voltage direct current(LVDC) distribution network through the power conversion system(PCS). Control power is required for the operation of the PCS. In general, controller power is supplied from AC power or DC power through switch mode power supply(SMPS). However, the conventional SMPS has a low input voltage, so development and research on high input voltage self-power suitable for LVDC is insufficient. In this paper, to develop Self-Power that can be used for LVDC, the characteristics of the conventional topology are analyzed, and a series-input single-output flyback converter using a flux-sharing transformer for high voltage is designed. The high input voltage Self-Power was designed in the DCM(discontinuous current mode) to reduce the switching loss and solve the problem of current dissipation. In addition, since it operates even at low input voltage, it can be applied to many applications as well as LVDC. The validity of the proposed high input voltage self-power is verified through experiments.