• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.8
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• pp.1774-1781
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• 1997

In this paper, we propose a full digital frequency and phase locked loop for CATV and HDTV receivers adopting VSB modulation. The CATV and HDTV receivers proposed by the Grand-Alliance in USA are ultilizing analog signal processing technology for carrier recovery. By the way, it is not a good architecture for the development of single chip ASIC operating in digital domain. To solve this problem while improving the performance, we first down convert the received r.f. signal to a near baseband signal for a low-rate AD converter and then we use digital signal processing techniques. The proposed system has the frequency pull-in range of -200 KHz +2.50 KHz. Moreover, it has the ability of adaptive loop bandwidth control according to the amount of frequency offset to improve the acquisition time while reducing the phase noise.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.11
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• pp.5208-5213
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• 2011

In this paper, we proposed a new direction finding(DF) technology using TDOA(time-difference of arrival) and PDOA(phase difference of arriving signal) method. The proposed technology has a good DF accuracy without DF ambiguity. TDOA or PDOA technology is used to the most of intelligence systems in 21 century. The principle of TDOA is to receive a signal with two parallel antennas, measure the time difference of arrival signal, and converse the time difference to the direction of incident signal. Those technology make a DF system small size but the DF accuracy is low into short antenna installation distance. The principle of PDOA is similar to TDOA except measuring the phase difference of arrival signal, These technology get a good DF accuracy in short antenna installation distance but have a DF ambiguity. The proposed DF method is simulated into DF system operation environment with noise, and has a good DF accuracy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.40-49
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• 2008

A Frequency synthesizer for mobile-DTV applications is implemented using $0.18{\mu}m$ CMOS process with 1.8V supply. PMOS transistors are chosen for VCO core to reduce phase noise. The measurement result of VCO frequency range is 800MHz-1.67GHz using switchable inductors, capacitors and varactors. We use varactor bias technique for the improvement of VCO gain linearity, and the number of varactor biasing are minimized as two. VCO gain deterioration is also improved by using the varactor switching technique. The VCO gain and interval of VCO gain are maintained as low and improved using the VCO frequency calibration block. The sigma-delta modulator for fractional divider is designed by the co-simualtion method for accuracy and efficiency improvement. The VCO, PFD, CP and LF are verified by Cadence Spectre, and the sigma-delta modulator is simulated using Matlab Simulink, ModelSim and HSPICE. The power consumption of the frequency synthesizer is 18mW, and the VCO has 52.1% tuning range according to the VCO maximum output frequency. The VCO phase noise is lower than -100dBc/Hz at 1MHz at 1MHz offset for 1GHz, 1.5GHz, and 2GHz output frequencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.2
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• pp.152-158
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• 2004

A low phase noise frequency synthesizer at X-Band which employs the subharmonic injection locking was designed and tested. The designed frequency synthesizer consists of a 1.75 GHz master oscillator - which also operates as a harmonic generator - and a 10.5 GHz slave oscillator. A 1.75 GHz master oscillator based on PLL technique used two transistors - one constitutes the active part of VCO and the other operates as a buffer amplifier as well as harmonic generator. The first stage operates a fixed locked oscillator and using the BJT transistor whose cutoff frequency is 45 GHz, the second stage is designed, operating as a harmonic generator. The 6th harmonic which is produced from the harmonic generator is injected into the following slave oscillator which also behaves as an amplifier having about 45 dB gain. The realized frequency synthesizer has a 7.4 V/49 mA, -0.5 V/4 mA of the low DC power consumption, 4.53 dBm of output power, and a phase noise of -95.09 dBc/Hz and -108.90 dBc/Hz at the 10 kHz and 100 kHz offset frequency, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.94-100
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• 2014

In this paper, a design of low power Current-Reuse Voltage Controlled Oscillator (VCO) which has wide tuning range about 1.95 GHz ~ 3.15 GHz is presented. Class-C type is applied to improve phase noise and 2-Step Auto Amplitude Calibration (AAC) is used for minimizing the imbalance of differential VCO output voltage which is main issue of Current-Reuse VCO. The mismatch of differential VCO output voltage is presented about 1.5mV ~ 4.5mV. This mismatch is within 0.6 % compared with VCO output voltage. Proposed Current-Reuse VCO is designed using CMOS $0.13{\mu}m$ process. Supply voltage is 1.2 V and current consumption is 2.6 mA at center frequency. The phase noise is -116.267 dBc/Hz at 2.3GHz VCO frequency at 1MHz offset. The layout size is $720{\times}580{\mu}m^2$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Korean Journal of Remote Sensing
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• v.21 no.4
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• pp.287-302
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• 2005

Digital Elevation Models (DEMs) were generated by ERS-l/2 and JERS-1 SAR interferometry in Daejon area, Korea. The quality of the DEM's was evaluated by the Ground Control Points (GCPs) in city area where GCPs were determined by GPS surveys, while in the mountain area with no GCPs, a 1:25,000 digital map was used. In order to minimize errors due to the inaccurate satellite orbit information and the phase unwrapping procedure, a Differential InSAR (DInSAR) was implemented in addition to the traditional InSAR analysis for DEM generation. In addition, DEMs from GTOPO30, SRTM-3, and 1:25,000 digital map were used for assessment the resolution of the DEM generated from DInSAR. 5-6 meters of elevation errors were found in the flat area regardless of the usage and the resolution of DEM, as a result of InSAR analyzing with a pair of ERS tandem and 6 pairs of JERS-1 interferograms. In the mountain area, however, DInSAR with DEMs from SRTM-3 and the digital map was found to be very effective to reduce errors due to phase unwrapping procedure. Also errors due to low signal-to-noise ratio of radar images and atmospheric effect were attenuated in the DEMs generated from the stacking of 6 pairs of JERS-1. SAR interferometry with multiple pairs of SAR interferogram with low resolution DEM can be effectively used to enhance the resolution of DEM in terms of data processing time and cost.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.974-982
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• 2009

Photomixing techniques beating two optical signals with different wavelengths and strong correlations are also very useful techniques to make a continuous wave(CW) signals in the range of millimeter(mm) and terahertz(THz) frequencies. An optical double sideband-suppressed carrier(DSB-SC) technique is one of the popular techniques to generate two optical signals with different wavelengths and strong correlations. DSB-SC signals with strong correlations are generated by a CW modulation of an optical carrier with a local oscillator and an optical modulator. In the previous parers related the DSB-SC for producing the CW signals within the range of mm and THz frequencies, there have been no reports why the optical carrier should suppress. In order to clear that, we have analyzed and measured the characteristics of the mm-wave CW signals made by the DSB-SC photomixing in this paper. From our analysis and measurement results, compared with the case of the DSB with the maximized optical carrier, the power and phase noise have improved about 23.9 dB and 21 dBc/Hz(@ 1 MHz offset frequency) in the case of the DSB with the minimized optical carrier (that is to say, the DSB-SC). Consequently, it is evident reason that the optical carrier should sufficiently suppress to obtain the mm-wave CW signals with the high power and low noise. This paper has given very helpful data to make mm- and THz-wave CW signals using photomixing techniques with the DSB-SC because the reason why the optical carrier should be suppressed is reported in this paper based on the numerical and experimental results.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.3
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• pp.211-219
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• 2014

This paper proposes a low voltage high current LLC resonant converter for Green PC. Green PC is composed of a lot of blade PCs, and it is a centralized system to manage them in computer center. Green PC should require that its power supplies have several characteristics such as low output voltage, high output current, and high power conversion efficiency. Conventional PSFB (Phase Shift Full Bridge) converter is usually used as DC/DC converter for computer power supply because it has high power conversion efficiency thanks to ZVS (Zero Voltage Switching) operation under middle and high load conditions. However, this converter has some problems such as large switching noise and limitation of ZVS operation under light load condition. In order to improve the performance of power supply for Green PC, a new power supply using popular high efficiency LLC resonant converter for low voltage and high current application is proposed in this paper. The proposed power supply has ZVS capability over the entire load range, thus resulting in good efficiency and high switching frequency. Experimental results verify the performance of the proposed power supply for Green PC using 2[kW] (19[V], 105[A]) rated prototype converter.

• Geophysics and Geophysical Exploration
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• v.25 no.4
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• pp.177-188
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• 2022

Recently, the application of distributed acoustic sensors (DAS), which can replace geophones and seismometers, has significantly increased along with interest in micro-seismic monitoring technique, which is one of the CO₂ storage monitoring techniques. A significant amount of temporally and spatially continuous data is recorded in a DAS monitoring system, thereby necessitating fast and accurate data processing techniques. Because event detection and seismic phase picking are the most basic data processing techniques, they should be performed on all data. In this study, a machine learning-based P, S wave phase picking algorithm was developed to compensate for the limitations of conventional phase picking algorithms, and it was modified using a transfer learning technique for the application of DAS data consisting of a single component with a low signal-to-noise ratio. Our model was constructed by modifying the convolution-based EQTransformer, which performs well in phase picking, to the ResUNet structure. Not only the global earthquake dataset, STEAD but also the augmented dataset was used as training datasets to enhance the prediction performance on the unseen characteristics of the target dataset. The performance of the developed algorithm was verified using K-net and KiK-net data with characteristics different from the training data. Additionally, after modifying the trained model to suit DAS data using the transfer learning technique, the performance was verified by applying it to the DAS field data measured in the Pohang Janggi basin.