• Journal of Korea Society of Industrial Information Systems
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• v.18 no.2
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• pp.35-40
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• 2013

In this paper, we propose a new image rejection receiver architecture using simultaneously the high-side and low-side injected LO signals. The proposed architecture has a lower noise figure (NF) performance and a higher linearity characteristic than the previous receiver architecture using a single LO signal. Also, the proposed receiver shows a higher IRR performance about 6dB than that of the previous Weaver image rejection architecture even though the same gain and phase errors between I-path and Q-path exist. To verify these characteristics, we derive an IRR formular of the proposed architecture as a function of mismatch parameters. And we demonstrate its formular's usefulness through the system simulation. Therefore, the proposed architecture will be widely used to implement the image rejection receiver due to its higher IRR performance.

• Journal of Power System Engineering
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• v.12 no.1
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• pp.13-19
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• 2008

In this study, a variable induction and exhaust system is applied to turbocharged diesel engine to improve the volumetric efficiency, especially, in a low and transient engine speed range where much of the pollutant matters are expelled out. The volumetric efficiency is known as one of the most important factor which affects significantly engine performance, fuel economy and further emission and noise level. As the torque increase with the engine speed up, the gas flow in an exhaust pipe become pulsating and then has an effect on boost up capacity of air charging into the cylinder and expelling capacity to atmosphere simultaneously. But at a low and idling speed, the pulsation effect was not so significant. Accordingly, resonator was employed to compensate their loss. The variable induction system consists of the secondary pipe, resonator, intercooler, and torque variance were examined with extended operating conditions. In the mean time, for interpretation and well understanding for the phenomena of wave action that arising during intake and exhaust process between turbocharger and variable intake system, the concept of the combined supercharging was introduced. Some of results are depicted which deal with a pressure history during valve events of induction process. Consequently, by the governing of these phase and amplitude of pulsating wave, it enables us to estimate and evaluate for the intake system performance and also, designing stage of the system layout.

• Journal of radiological science and technology
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• v.38 no.2
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• pp.107-114
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• 2015

The purpose is reducing radiation dose while maintaining of image quality in liver dynamic CT(LDCT) scan, by protocols generally used and the tube voltage set at a low level protocol compared to the radiation dose and image quality. The target is body mass index, 18.5~24 patients out of 40 patients who underwent the ACT(abdominal CT). Group A(tube voltage : 120kVp, SAFIRE strength 1) of 20 people among 40 people, to apply the general abdominal CT scan protocol, group B(tube voltage : 100kVp, apply SAFIRE strength 0~5) was 20 people, set a lower tube voltage. Image quality evaluation was setting a region of interest(ROI) in the liver parenchyma, aorta, superior mesenteric artery (SMA), celiac trunk, visceral fat of arterial phase. In the ROI were compared by measuring the noise, signal to noise ratio(SNR), contrast to noise ratio(CNR), CT number. In addition, qualitative assessments to evaluate two people in the rich professional experience in Radiology by 0-3 points. We compared the total radiation dose, dose length product(DLP) and effective dose, volume computed tomography dose index(CTDIvol). The higher SAFIRE in the tube voltage 100 kVp, noise is reduced, CT number was increased. Thus, SNR and CNR was increased higher the SAFIRE step. Compared with the tube voltage 120kVp, noise, SNR, CNR was most similar in SAFIRE strength 2 and 3. Qualitative assessment SAFIRE strength 2 is the most common SAFIRE strength 2 the most common qualitative assessment, if the tube voltage of 100kVp when the quality of the images better evaluated was SAFIRE strength 1. Dose was reduced from 21.69%, in 100kVp than 120kVp. In the case of a relatively high BMI is not LDCT scan, When it is shipped from the factory tube voltage is set higher, unnecessary radiation exposure when considering the reality that is concerned, when according to the results of this study, set a lower tube voltage and adjust the SAFIRE strength to 1 or 2, the radiation without compromising image quality amount also is thought to be able to be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.23-30
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• 2002

The PVDF (Polyvinylidene Fluoride) thin film having P phase is prepared by the vacuum deposition with applying the electric field and its pyroelectric properties are studied by using a dynamic method to examine the possibility of the application to the pyroelectric IR sensor. The pyroelectric responses of the PVDF thin film are characterized as the frequency dispersion in both low and high modulation frequency regions, and their frequency dependences are observed. In the low frequency region (2~10Hzz), the polarization can easily rotate with the increase of modulation frequency and show the maximum since the reorientation rate of domains is higher than the modulation frequency. On the other hand, in the high frequency region (100~1000Hz), the pyroelectric response decreases as the frequency increases, because the reorienatation rate of domains is suppressed and thus, the change of polarization decreases. Pyroelectric coefficient, figure of merits for noise equivalent power and detectivity of the PVDF thin film are measured as 3.2$\times$10$^{-10}$ C/$\textrm{cm}^2$.K, 2.34$\times$10$^{-10}$ C.cm/J and 1.32$\times$10$^{-9}$ C.cm/J, respectively. Also, the noise equivalent and the detectivity are 1.66$\times$10$^{-7}$ W/H $z^{$\sfrac{1}{2}$}$, 6.03$\times$10$^{5}$ cm.H $z^{$\sfrac{1}{2}$}$W, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.8
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• pp.593-602
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• 2020

Power cables installed in domestic factories or underground can cause accidents depending on the manufacturing process, installation, and environmental conditions during use. When an accident occurs in a power cable, it can cause enormous economic loss and social confusion. Hence, the importance of preventive management of the cable through diagnosis is increasing to prevent it. Therefore, in this paper, a diagnostic sample cable was produced by simulating a part that could be a problem due to the installation, manufacturing defects, or deterioration of cables that can occur in the field. Dielectric loss Tangent (tan 𝛿; TD), and Partial Discharge(PD) tests were performed. Partial discharge and AC (60Hz) withstand voltage equipment using High-Frequency Current Transformer (HFCT) were applied After applying a VLF (Very Low Frequency) power supply with a frequency of 0.1Hz was applied. As a result, B and C phase defect samples at a 2.0U₀ voltage through the VLF could measure the internal partial discharge in the A-phase normal sample cable from the noise at a 0.5U₀ to 2.0U₀ voltage. In addition, the 1.5U₀ voltage was measured through the AC (60Hz) withstand voltage equipment of the commercial frequency to verify its effectiveness. Partial discharge in the run-off state was measured at a voltage of 1.0U₀, and there was a risk when installing the equipment. AC power equipment showed a difficulty of movement by volume or weight. The diagnostic method, through the VLF of the quadrant state, revealed its safety and effectiveness.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.5
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• pp.613-623
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• 2012

In this paper, we present an ultra miniaturized voltage tuned oscillator, with HMIC-type amplifier and phase shifter, using LTCC artificial dielectric resonator. ADR which consists of periodic conductor patterns and stacked layers has a smaller size than a dielectric resonator. The design specification of ADR is obtained from the design goal of oscillator. The structure of the ADR with a stacked circular disk type is chosen. The resonance characteristic, physical dimension and stack number are analyzed. For miniaturization of ADRO, the ADR is internally implemented at the upper part of the LTCC substrate and the other circuits, which are amplifier and phase shifter are integrated at the bottom side respectively. The fabricated ADRO has ultra small size of $13{\times}13{\times}3mm^3$ and is a SMT type. The designed ADRO satisfies the open-loop oscillation condition at the design frequency. As a results, the oscillation frequency range is 2.025~2.108 GHz at a tuning voltage of 0~5 V. The phase noise is $-109{\pm}4$ dBc/Hz at 100 kHz offset frequency and the power is $6.8{\pm}0.2$ dBm. The power frequency tuning normalized figure of merit is -30.88 dB.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.55-64
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• 2006

This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and l.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is $3.3mm^2$.

• ETRI Journal
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• v.26 no.3
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.6
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• pp.854-862
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• 1993

All of the CMOS analog and analog-digital systems have composed with several basic circuits, and among them, a important block, the amplifier part can affect the system's performance, Therefore, according to the uses in the system, the amplifier circuit have designed as various architectures (high-gain, low-noise, high-speed circuit, etc...). In this paper, we have proposed a new CMOS differential amplifier circuit. This circuit is differential to single ended input stage comprised of CMOS complementary gain circuits having internally biasing configurations. These architectures can be achieved the high gain and reduced the transistors for biasing. As a results of SPICE simulation with the standard $1.5{\mu}m$ processing parameter, the gain of the proposed circuit have a doubly value of the typical circuit's while maintaining other characteristics(phase margin, offset, etc...). And the proposed circuit is applicated in a simple CMOS comparator which has the settling time in 7nsec(CL=1pF) and the igh output swing $({\pm}4.5V)$.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.335-338
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• 2004

We suggest Q-band MEMS MIMIC (Millimeter wave Monolithic Integrated Circuit) HEMT Oscillator using DAML (Dielectric-supported Airgapped Mcrostrip Line) structure. We elevated the signal lines from the substrate using dielectric post, in order to reduce the substrate dielectric loss and obtain low losses at millimeter-wave frequency. These DAML are composed with heist of $10\;{\mu}m$ and post size with $20\;{\mu}m\;{\times}\;20\;{\mu}m$. The MEMS oscillator was successfully integrated by the process of $0.1\;{\mu}m$ GaAs PHEMTs, CPW transmission line and DAML. The phase noise characteristic of the MEMS oscillator was improved more than 7.5 dBc/Hz at a 1 MHz offset frequency than that of the CPW oscillator And the high output power of 7.5 dBm was measured at 34.4 GHz.