• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• International journal of advanced smart convergence
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• v.10 no.3
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• pp.81-88
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• 2021

This paper proposes two types of subharmonic RF receiver front-end (called LMV) where, in a single stage, quadrature voltage-controlled oscillator (QVCO) is stacked on top of a low noise amplifier. Since the QVCO itself plays the role of the single-balanced subharmonic mixer with the dc current reuse technique by stacking, the proposed topology can remove the RF mixer component in the RF front-end and thus reduce the chip size and the power consumption. Another advantage of the proposed topologies is that many challenges of the direct conversion receiver can be easily evaded with the subharmonic mixing in the QVCO itself. The intermediate frequency signal can be directly extracted at the center taps of the two inductors of the QVCO. Using a 65 nm complementary metal oxide semiconductor (CMOS) technology, the proposed subharmonic RF front-ends are designed. Oscillating at around 2.4 GHz band, the proposed subharmonic LMVs are compared in terms of phase noise, voltage conversion gain and double sideband noise figure. The subharmonic LMVs consume about 330 ㎼ dc power from a 1-V supply.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.1-10
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• 2004

This paper presents a navigation garde capacitive microaccelerometer, whose low-noise high-resolution detection capability is achieved by a new electrode design based on a high-amplitude anti-phase sense voltage. We reduce the mechanical noise of the microaccelerometer to the level of 5.5$\mu\textrm{g}$/(equation omitted) by increasing the proof-mass based on deep RIE process of an SOI wafer. We reduce the electrical noise as low as 0.6$\mu\textrm{g}$/(equation omitted) by using an anti-phase high-amplitude square-wave sense voltage of 19V. The nonlinearity problem caused by the high-amplitude sense voltage is solved by a new electrode design of branched finger type. Combined use of the branched finger electrode and high-amplitude sense voltage generates self force-balancing effects, resulting in an 140％ increase of the bandwidth from 726㎐ to 1,734㎐. For a fixed sense voltage of 10V, the total noise is measured as 2.6$\mu\textrm{g}$/(equation omitted) at the air pressure of 3.9torr, which is the 51％ of the total noise of 5.1$\mu\textrm{g}$/(equation omitted) at the atmospheric pressure. From the excitation test using 1g, 10㎐ sinusoidal acceleration, the signal-to-noise ratio of the fabricated microaccelerometer is measured as 105㏈, which is equivalent to the noise level of 5.7$\mu\textrm{g}$/(equation omitted). The sensitivity and linearity of the branched finger capacitive microaccelerometer are measured as 0.638V/g and 0.044％, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.385-388
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• 1996

A time delay controller with state feedback is proposed for azimuth motion control of the frictionless positioning device which is subject to the variations of inertia in the presence of measurement noise. The time delay controller, which is combined with a low-pass filter to attenuate the effect of measurement noise, ensures the asymptotic stability of the closed loop system. It is found that the low-pass filter tends to increase the robustness in the design of time delay controller as well as the gain and phase margins of the closed loop system. Numerical and experimental results support that the proposed controller guarantees a good tracking performance irrespective of the variation of inertia and the presence of measurement noise.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.4
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• pp.538-550
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• 1998

The variable frequency and variable voltage AC source made by a conventional inverter which is composed of power semi-conductors includes much noises in sine wave due to high frequency switching of DC source. In this paper the 3rd low pass LC filter for a variable speed 3 phase induction motor driven by a full bridge inverter is introduced to solve the EMI problem by serious noise current. The utility of a modified 3rd order Butterworth LC filter is confirmed through FFT analysis of sine waves and noiseless ACsource can be obtained by the proposed LC filter. The speed of a 3 phase induction motor driven by a full bridge inverter with a LC filter is satisfactorily controlled by a digital PID controller under the condition of stepwise load and setpoint changes.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.48 no.1
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• pp.73-79
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• 2020

Modern radar system requires high spectral purity and low phase noise characteristics for very low RCS target detection and high resolution SAR (Synthetic Aperture Radar) image. This paper presents a new X-band high stable frequency synthesizer for high performance radar system, which combines DAS (Direct Analog Synthesizer) and DDS (Direct Digital Synthesizer) techniques, in order to cope with very low phase noise and high frequency agility requirements. This synthesizer offers more than 10% operating bandwidth in X-band frequency and fast agile time lower than 1 usec. Also, the phase noise at 10kHz offset is lower than -136dBc/Hz, which shows an improvement of more than 10dB compared to the current state of art frequency synthesizer. This architecture can be applied to L-band and C-band application as well. This frequency synthesizer is able to used in modern AESA (Active Electronically Scanned Array) radar system and high resolution SAR application.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2000.06a
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• pp.606-611
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• 2000

It has been noted that the low frequency absorption coefficient of a porous sample placed in a standing wave tube is affected by the nature of the sample's edge constraint. The edge constraint has the effect of stiffening the solid phase of the sample, which itself can be strongly coupled to the material's fluid phase, and hence the incident sound field, by viscous means at low frequencies. In recent work it has also been shown that such a circumferential constraint causes the low frequency transmission loss of a layer of fibrous material to approach a finite low frequency limit that is proportional to the flow resistance of the layer and which is substantially higher than that of an unconstrained sample of the same material. However, it was also found that the benefit of the circumferential edge constraint was reduced in a transitional frequency range by a shearing resonance of the sample. Here it will be shown that the effect of that resonance can be mitigated or eliminated by adding additional axial and radial constraints running through the sample. It will also be shown that the constraint effect can be modeled closely by using a finite element procedure based on the Biot poroelastic theory. Implications for low frequency barrier design are also discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.515-525
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• 2014

In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency