• Proceedings of the Korea Society for Industrial Systems Conference
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• 2003.11a
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• pp.481-486
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• 2003

RF 전파는 신호레벨이 비교적 작고 간섭 현상에 매우 민감한 특성을 가지고 있다. 따라서 이러한 미소한 입력전파의 수신시 수신기 전체의 감도를 높이고 잡음을 줄일 목적으로 사용되는 고주파 증폭기가 저잡음 증폭기이다. 본 논문에서는 FET 증폭기를 이용한 LNA설계시 직렬 궤환에 의한 최소잡음과 최소입력정재파비의 최적 설계 파라미터를 검증한다. LNA의 기본적 특성 분석과 IMT-2000 구역의 1. 9GHZ대의 휴대단말기용 LNA와 블루투스용 2.4GHz대의 LNA 그리고, 지능형교통시스템에 응용되는 5.8GHz대의 단거리전용통신 LNA를 구현하고 각 주파수별로 특성이 다른 BJT, FET 증폭기를 적용하여 설계하고 성능 분석 및 최적의 파라미터를 도출하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.408-415
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• 2007

A switched-gain controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8\;GHz$ UWB system. In high gain mode, measurement shows a power gain of 12.5 dB, an input IP3 of 0 dBm, while consuming only 8.13 mA of current. In low gain mode, measurement shows a power gain of -8.7 dB, an input IP3 of 9.1 dBm, while consuming only 0 mA of current.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.48-53
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• 2008

In this paper, we developed the MMIC low noise amplifier using 100 nm metamorphic HEMTs technology in combination with coplanar circuit topology for 94 GHz applications. The $100nm\times60{\mu}m$ MHEMT devices for the MMIC LNA exhibited DC characteristics with a drain current density of 655 mA/mm, an extrinsic transconductance of 720 mS/mm. The current gain cutoff frequency $(f_T)$ and maximum oscillation frequency $(f_{max})$ were 195 GHz and 305 GHz, respectively. The realized MMIC LNA represented $S_{21}$ gain of 14.8 dB and noise figure of 4.6 dB at 94 GHz with an over-all chip size of $1.8mm\times1.48mm$.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.313-316
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• 2005

In this paper, an active antenna for terrestrial DMB(Digital Multimedia Broadcasting) repeater is designed. This active antenna is consist of receiving antenna and LNA(Low Noise Amplifier), A receiving antenna fed by using a microstrip line and radiation part is designed with rectangular spiral structure. An receiving antenna with frequency range of 162$\sim$212MHz, gain of -10dBi and LNA with gain of 20dBi, noise figure of 2.2 at frequency range for T-DMB are achieved.

• Proceedings of the KIEE Conference
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• 2008.05a
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• pp.151-152
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• 2008

In this paper, a dual band LNA (Low Noise Amplifier) with a matching circuit using varactor diode is designed for 912MHz and 2450MHz RFID system. The operating frequency is controlled by the bias voltage applied to the varactor diode. The measured results demonstrate that gain is 13.6dB and 6.8dB at 912MHz and 2450MHz. The measured NF (Noise Figure) is 1.4dB and 3.1dB at 912MHz and 2450MHz, respectively.

• Journal of IKEEE
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• v.23 no.3
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• pp.917-924
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• 2019

This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6A
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• pp.697-704
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• 2004

This paper describes the design and fabrication of an MMIC variable gain LNA for 5GHz wireless LAN applications, using 0.5${\mu}{\textrm}{m}$ gate length GaAs MESFET transistors. The advantages of high gain and low noise performance of E-MESFETS and excellent linear performance of D-MESFETS are combined as a cascode topology in this design. Behavioral model equations are derived from the MESFET nonlinear current voltage characteristics by using Turlington's asymptote method in a cascode configuration. Using the behavioral model equations, a 4${\times}$50${\mu}{\textrm}{m}$ E-MESFET as a common source amplifier and a 2${\times}$50${\mu}{\textrm}{m}$ D-MESFET as a common gate amplifier are determined for the cascode amplifier. The fabricated variable gain LNA shows a noise figure of 2.4dB, variable gain range of more than 17dB, IIP3 of -4.8dBm at 4.9GHz, and power consumption of 12.8mW.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.894-897
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• 2003

Recently, the rapid growth of mobile radio system has led to an increasing demand of low-cost high performance communication IC's. In this paper, we have designed RF front end for wireless LAN receiver employ zero-IF architecture. A low-noise amplifier (LNA) and double-balanced mixer is included in a front end. The zero-IF architecture is easy to integrate and good for low power consumption, so that is coincided to requirement of wireless LAN. But the zero-IF architecture has a serious problem of large offset. Image-reject mixer is a good structure to solve offset problem. Using offset compensation circuit is good structure, too. The front end is implemented in 0.25 ${\mu}m$ CMOS technology. The front end has a noise figure of 5.6 dB, a power consumption of 16 mW and total gain of 22 dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.106-113
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• 2003

In this paper, we proposed low noise amplifier for 2.4GHz ISM frequency with CMOS technology. The property of noise and gain is improved by cascode architecture. The architecture, which common source output of cascode is connected to input of parallel MOS, reduce IM. The LNA results based on Hynix 0.35${\mu}{\textrm}{m}$ 2poly 4metal CMOS processor with a 3.3V supply. It achieves a gain of 13dB, noise figure of 1.7dB, IP3 of 8dBm, Input/output matching of -31dB/-28dB, reverse isolation of -25dB. and power dissipation of 4.7mW with HSPICE simulation. The size of layout is smaller than 2 ${\times}$ 2mm with Mentor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.