• ETRI Journal
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• v.28 no.5
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• pp.672-675
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• 2006

The effect of block interleaving in a low density parity check (LDPC)-turbo concatenated code is investigated in this letter. Soft decoding can be used in an LDPC code unlike the conventional Reed-Solomon (RS) code. Thus, an LDPC-turbo concatenated code can show better performance than the conventional RS-turbo concatenated code. Furthermore, the performance of an LDPC-turbo code can be improved by using a block interleaver between the LDPC and turbo code. The average number of iterations in LDPC decoding can also be reduced by a block interleaver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9C
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• pp.801-809
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• 2007

LDPC Low Density Parity Check) code, which is an error correcting code determined to be applied to the 4th generation mobile communication systems, requires a heavy computational complexity due to iterative decodings to achieve a high BER performance. This paper proposes an algorithm to reduce the number of decoding iterations to increase performance of the decoder in decoding latency and power consumption. Measuring changes between the current decoded LLR values and previous ones, the proposed algorithm predicts directions of the value changes. Based on the prediction, the algorithm inverts the sign bits of the LLR values to speed up convergence, which means parity check equation is satisfied. Simulation results show that the number of iterations has been reduced by about 33% without BER performance degradation in the proposed decoder, and the power consumption has also been decreased in proportional to the amount of the reduced decoding iterations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.744-749
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• 2013

We propose soft user data input on LDPC codes with parity encoded by the (1, 7) run length limited (RLL) code for perpendicular magnetic recording channel. The user data are encoded by maximum transition run (MTR) (3;11) code. In order to minimize the loss of code rate, the (1, 7) RLL code only encode the parity of LDPC. Also, to increase performance, we propose only user data part applied soft output Viterbi algorithm (SOVA). The performance using the SOVA showed good performance lower than 26 dB. In contrast, it showed worse performance high than 26 dB. This is because of incorrect soft information by high jitter noise and two different input types for LDPC decoder.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2006.11a
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• pp.229-232
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• 2006

본 논문은 AWGN 채널상의 Single Parity Check(SPC) 다차원 product부호에서 LDPC(Low Density Parity Check)부호를 이용한 오류 정정의 성능을 제시한다. 기존 방법인 터보 부호 방식을 이용한 오류 정정과 비교하여 LDPC부호가 갖는 장점을 기술하고 실험을 통해 LDPC 부호를 이용한 오류 정정 성능도 터보부호와 대등함을 보인다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.11
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• pp.2637-2642
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• 2015

The low-density parity check(LDPC) code is being widely used due to its outperformed error-correction ability. The decoder of the quasi-cyclic LDPC(QC-LDPC) codes, a kind of LDPC codes, requires a multi-size cyclic shifter(MSCS) performing rotation of various sizes. The MSCS can be implemented with a Benes network, which requires a $3{\times}3$ switch if the number of data to be rotated is a multiple of 3. This paper proposes a control signal generation with lower complexity and a faster $3{\times}3$ switch. For the experiment, the proposed schemes are applied to the MSCS of an IEEE 802.16e WiMAX QC-LDPC code decoder. The result shows that the delay is reduced by about 8.7%.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.5 s.311
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• pp.68-75
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• 2006

Multimedia fingerprinting protects multimedia content from illegal redistribution by uniquely marking every copy of the content distributed to each user. Differ from a symmetric/asymmetric scheme, fingerprinting schemes, only regular user can know the inserted fingerprint data and the scheme guarantee an anonymous before recontributed data. In this paper, we present a scheme which is the algorithm using LDPC(Low Density Parity Check) for detection of colluded multimedia fingerprint and correcting errors. This proposed scheme is consists of the LDPC block, Hopfield Network and the algorithm of anti-collusion code generation. Anti-collusion code based on BIBD(Balanced Incomplete Block Design) was made 100% collusion code detection rate about the linear collusion attack(average, AND and OR) and LD% block for the error bits correction confirmed that can correct error until AWGN 0dB.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.11
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• pp.2465-2473
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• 2011

This paper describes a circuit-level optimization of DFU(decoding function unit) for LDPC decoder which is used in wireless communication systems including WiMAX and WLAN. A new design of DFU based on sign-magnitude arithmetic instead of two's complement arithmetic is proposed, resulting in 18% reduction of gate count for 96 DFUs array used in mobile WiMAX LDPC decoder. A multi-mode LDPC decoder for mobile WiMAX standard is designed using the proposed DFU. The LDPC decoder synthesized using a 0.18-${\mu}m$ CMOS cell library with 50 MHz clock has 268,870 gates and 71,424 bits RAM, and it is verified by FPGA implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4C
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• pp.299-304
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• 2008

For perpendicular magnetic recording channels, it is hard to expect improving the performance by using the PRML or NPML. Hence, we exploit LDPC code to improve the performance. In this paper, we examine a single message-passing detector/decoder matched to the combination of a perpendicular magnetic recording channel detector and an LDPC code decoder. We examine the performance of channel iteration with joint LDPC code on perpendicular magnetic recording channel, and simplify the complexity of the message-passing detector algorithm.

• ETRI Journal
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• v.31 no.5
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• pp.619-621
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• 2009

In this letter, we study the influence of receiver imperfections on bit error rate (BER) degradations in detecting low-density parity-check coded multilevel phase-shift keying signals transmitted over a Rician fading channel. Based on the analytical system model which we previously developed using Monte Carlo simulations, we determine the BER degradations caused by the simultaneous influences of stochastic phase error, quadrature error, in-phase-quadrature mismatch, and the fading severity.