• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10C
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• pp.1363-1369
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• 2004

LDPC(Low Density Parity Check) codes are described by bipartite graphs with bit nodes and parity-check nodes. Tanner derived minimum distance bounds of the regular LDPC code in terms of the eigenvalues of the associated adjacency matrix. In this paper we generalize the Tanner's results. We derive minimum distance bounds applicable to both regular and blockwise-irregular LDPC codes. The first bound considers the relation between bit nodes in a minimum-weight codeword, and the second one considers the connectivity between parity nodes adjacent to a minimum-weight codeword. The derived bounds make it possible to describe the distance property of the code in terms of the eigenvalues of the associated matrix.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.6
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• pp.471-478
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• 2013

Powerful error control and increase in the number of bits per symbol should be provided for future high-quality communication systems. Each message bit may have different importance in multimedia data. Hence, UEP(unequal error protection) may be more efficient than EEP(equal error protection) in such cases. And the LDPC(low-density parity-check) code shows near Shannon limit error correcting performance. Therefore, the effect of UEP with LDPC codes is analyzed for high-quality message data in this paper. The relationship among MSE(mean square error), BER(bit error rate) and the number of bits per symbol is analyzed theoretically. Then, total message bits in a symbol are classified into two groups according to importance to prove the relationship by simulation. And the UEP performance is obtained by simulation according to the number of message bits in each group with the constraint of a fixed total code rate and codeword length. As results, the effect of UEP with the LDPC codes is analyzed by MSE according to the number of bits per symbol, the ratio of the message bits, and protection level of the classified groups.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.10a
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• pp.722-725
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• 2010

In this paper, BER performance and error convergence speed of layered LDPC(Low Density Parity Check) decoder which supports IEEE 802.16e WiMAX standard is analyzed, and optimal design conditions for hardware implementation are derived. A LDPC decoder is modeled and simulated at AWGN channel with QPSK modulation by Matlab. The parity check matrix(PCM) for IEEE 802.16e standard which has block lengths of 576, 1440, 2304 and code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 are used. Fixed-point simulation results show that fixed-point bit-width should be more than 8 bits for acceptable decoding performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5A
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• pp.436-444
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• 2005

Unitary matrix modulation (UMM) is investigated in multiple antennas system that is called unitary space-time modulation (USTM). In an OFDM, the diagonal components of UMM with splitting over the coherence bandwidth (UMM-S/OFDM) have been proposed. Recently LDPC code is strongly attended and studied due to simple decoding property with good error correction property. In this paper, we propose LDPC coded UMM-S/OFDM for increasing the system performance. Our proposed system can obtain frequency diversity using UMM-S/OFDM like USTM/OFDM, and large coding gain using LDPC code. The superior characteristics of the proposed UMM-S/OFDM are demonstrated by extensive computer simulations in multi-path Rayleigh fading channel.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.92-96
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• 2008

Practical communication systems need to operate at various different rates. This paper describes and analyzes low-density parity check codes for various different rates. From a specific mother code, it allows LDPC codes for different rate. The advantage of this technique is that each different rate LDPC codes have a same block length as mother code though the rate changes so it can make up for the weak points of puncturing and shortening which reduce their block length as the rate changes. Row-splitting method is to split the row, so that the rate changes from a higher rate to lower rate and cause of its own property, it can overcome the defect of row-combining method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.175-180
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• 2009

When we apply the LDPC code for high density optical storage channel, it is necessary to make an algorithm that the modulation code decoder must feed the LDPC decoder soft-valued information because LDPC decoder exploits soft values using the soft input. Therefore, we propose the soft-input soft-output run-length limited 17PP decoding algorithm and compare performance of LDPC codes. Consequently, we found that the proposed soft-input soft-output decoding algorithm using 17PP is 0.8dB better than the soft-input soft-output decoding algorithm using (1, 7) RLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.405-409
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• 2009

In this paper, the effects of LLR (Log-Likelihood Ratio) approximation on LDPC (Low-Density Parity-Check) decoder performance are analyzed, and optimal design conditions of LDPC decoder are derived. The min-sum LDPC decoding algorithm which is based on an approximation of LLR sum-product algorithm is modeled and simulated by MATLAB, and it is analyzed that the effects of LLR approximation bit-width and maximum iteration cycles on the bit error rate (BER) performance of LDCP decoder. The parity check matrix for IEEE 802.11n standard which has block length of 1,944 bits and code rate of 1/2 is used, and AWGN channel with QPSK modulation is assumed. The simulation results show that optimal BER performance is achieved for 7 iteration cycles and LLR bit-width of (7,5).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.179-187
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• 2012

In this paper, we propose an adaptive DFE (Decision Feedback Equalizer) based on LDPC (Low Density Parity Check) code for phase noise suppression and performance improvement. The proposed equalizer in this paper is applied for wireless repeater system. So as to meet ever increasing requirements on higher wireless access data rate and better quality of service (QoS), the wireless repeater system has been studied. The echo channel and RF impairments such as phase noise produce performance degradation. In order to remove echo channel and phase noise, we suggest a novel adaptive DFE equalizer based on LDPC code. The proposed equalizer helps to compensate RF impairments and improve the performance significantly better than used independently. In addition, proposed equalizer has less iteration number of LDPC code. So, the proposed equalizer system has low complexity.