• IEIE Transactions on Smart Processing and Computing
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• v.6 no.3
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• pp.210-219
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• 2017

This paper proposes a modified min-max algorithm (MMMA) for nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) codes and an efficient parallel block-layered decoder architecture corresponding to the algorithm on a graphics processing unit (GPU) platform. The algorithm removes multiplications over the Galois field (GF) in the merger step to reduce decoding latency without any performance loss. The decoding implementation on a GPU for NB-QC-LDPC codes achieves improvements in both flexibility and scalability. To perform the decoding on the GPU, data and memory structures suitable for parallel computing are designed. The implementation results for NB-QC-LDPC codes over GF(32) and GF(64) demonstrate that the parallel block-layered decoding on a GPU accelerates the decoding process to provide a faster decoding runtime, and obtains a higher coding gain under a low $10^{-10}$ bit error rate and low $10^{-7}$ frame error rate, compared to existing methods.

• ETRI Journal
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• v.39 no.3
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• pp.319-325
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• 2017

The decoding process of a quasi-cyclic low-density parity check code requires a unique type of rotator. These rotators, called multi-size cyclic-shifters (MSCSs), rotate input data with various sizes, where the size is the amount of data to be rotated. This paper proposes a low-complexity MSCS structure for the case when the sizes have a nontrivial common divisor. By combining the strong points of two previous structures, the proposed structure achieves the smallest area. The experimental results show that the area reduction was more than 14.7% when the proposed structure was applied to IEEE 802.16e as an example.

• Journal of Communications and Networks
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• v.10 no.1
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• pp.5-9
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• 2008

Researchers have investigated many upper bound techniques applicable to error probabilities on the maximum likelihood (ML) decoding performance of turbo-like codes and low density parity check (LDPC) codes in recent years for a long codeword block size. This is because it is trivial for a short codeword block size. Previous research efforts, such as the simple bound technique [20] recently proposed, developed upper bounds for LDPC codes and turbo-like codes using ensemble codes or the uniformly interleaved assumption. This assumption bounds the performance averaged over all ensemble codes or all interleavers. Another previous research effort [21] obtained the upper bound of turbo-like code with a particular interleaver using a truncated union bound which requires information of the minimum Hamming distance and the number of codewords with the minimum Hamming distance. However, it gives the reliable bound only in the region of the error floor where the minimum Hamming distance is dominant, i.e., in the region of high signal-to-noise ratios. Therefore, currently an upper bound on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix cannot be calculated because of heavy complexity so that only average bounds for ensemble codes can be obtained using a uniform interleaver assumption. In this paper, we propose a new bound technique on ML decoding performance for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix using ML estimated weight distributions and we also show that the practical iterative decoding performance is approximately suboptimal in ML sense because the simulation performance of iterative decoding is worse than the proposed upper bound and no wonder, even worse than ML decoding performance. In order to show this point, we compare the simulation results with the proposed upper bound and previous bounds. The proposed bound technique is based on the simple bound with an approximate weight distribution including several exact smallest distance terms, not with the ensemble distribution or the uniform interleaver assumption. This technique also shows a tighter upper bound than any other previous bound techniques for turbo-like code with a particular interleaver and LDPC code with a particular parity check matrix.

• Journal of Communications and Networks
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• v.16 no.6
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• pp.639-644
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• 2014

In low-density parity-check (LDPC) coded multiple-input multiple-output (MIMO) communication systems, probabilistic information are exchanged between an LDPC decoder and a MIMO detector. TheMIMO detector has to calculate probabilistic values for each bit which can be very complex. In [1], the authors presented a class of linear block codes named low-density MIMO codes (LDMC) which can reduce the complexity of MIMO detector. However, this code only supports the outer-iterations between the MIMO detector and decoder, but does not support the inner-iterations inside the LDPC decoder. In this paper, a new approach to construct LDMC codes is introduced. The new LDMC codes can be encoded efficiently at the transmitter side and support both of the inner-iterations and outer-iterations at the receiver side. Furthermore they can achieve the design rates and perform very well over MIMO channels.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.7
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• pp.1-8
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• 2008

Low Density Parity Check codes(LDPC) are recently focused on communication systems due to its good performance. The standard of WiBro has also included LDPC codes as a channel coding. The weak point of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which limit throughput. In this paper, we propose semi-parallel architecture by using cyclic shift registers and exclusive-OR without conventional Matrix Vector Multipliers over the standard parity check matrices with Circulant Permutation Matrices(CPM). Furthermore, multi-rate encoder is designed by using proposed architecture. Our encoder with multi-rate for IEEE 802.16e LDPC has lower clock cycles and higher throughput.

• Journal of Communications and Networks
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• v.12 no.5
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• pp.406-410
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• 2010

This paper presents an approach to the construction of non-binary quasi-cyclic (QC) low-density parity-check (LDPC) codes based on multiplicative groups over one Galois field GF(q) and Euclidean geometries over another Galois field GF($2^S$). Codes of this class are shown to be regular with girth $6{\leq}g{\leq}18$ and have low densities. Finally, simulation results show that the proposed codes perform very wel with the iterative decoding.

• Journal of Korea Multimedia Society
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• v.9 no.6
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• pp.728-734
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• 2006

Carrier interferometry code is considered as a promising scheme that provides significant performance improvement via frequency diversity effect. Space-time coding is commonly employed to achieve a performance gain through space diversity. The combination of these techniques and forward error correction coding will lead to enhanced system capacity and performance. This paper presents a low-density parity check (LDPC) coded space-time orthogonal frequency division multiplexing (OFDM) transmission scheme with carrier interferometry code for high-capacity and high-performance mobile multimedia communications. Computer simulations demonstrate that the proposed mobile multimedia transmission system offers a considerable performance improvement of approximately 9dB in terms of Eb/No in the Rayleigh fading channel with relatively low delay spread, in comparison with space-time OFDM. Performance gains are further increased, comparing with traditional OFDM systems.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Journal of the Korean Mathematical Society
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• v.48 no.3
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• pp.475-486
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• 2011

The paper deals with repeated low-density burst error detecting codes with a specied weight or less. Linear codes capable of detecting such errors have been studied. Further codes capable of correcting and simultaneously detecting such errors have also been dealt with. The paper obtains lower and upper bounds on the number of parity-check digits required for such codes. An example of such a code has also been provided.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39C no.8
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• pp.637-642
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• 2014

In this paper, we propose a efficient shift index searching algorithm for design of the block LDPC codes. It is combined with the message-passing based cycle search algorithm and ACE algorithm. We can determine the shift indices by ordering of priority factors which are effect on the LDPC code performance. Using this algorithm, we can construct the LDPC codes with low complexity compare to trellis-based search algorithm and save the memory for storing the parity check matrix.