• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.8
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• pp.841-849
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• 1992

In power system operation, the stability of synchronous machine has been recognized one of the most important things. AESOPS program developed by EPRI in U.S.A. is a frequency domain analysis program in power system stability and it computes the electro-mechanical oscillation mode. This paper presents how to analyze the power system small signal stability problem efficiently by uusing the AESOPS program and analyze the various factors affecting the damping characteristics of these oscillations in KEPCO power system of 1986 with pumped-storage plant. To reduce the computing time and efforts, selecting the poorly-damped oscillation mode and clustering technique have been used. The characteristics of load, the amount of power flow on the transmission line and the gain of exciter have a significant effects on the damping of the system while the governing system has only a minor one. With the Power System Stabilizers, the stability of the power system has been improved.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• IEIE Transactions on Smart Processing and Computing
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• v.6 no.2
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• pp.129-132
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• 2017

A conventional pulse oximeter has high power consumption; thus, its mobility is severely limited. In this paper, we discuss the drawbacks of the existing pulse oximeters and propose a new ultra-low-power pulse oximeter that supports wireless data transmission for remotely monitoring vital signs, such as peripheral capillary oxygen saturation (SpO2) and beats per minute (BPM). We could notably reduce power consumption by using a low-frequency single clock in all well-customized modules. Also, our device is publicly certified, and thus, possibly engaged in clinical trials for commercial use.

• Journal of KIISE:Information Networking
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• v.30 no.2
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• pp.179-188
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• 2003

Advances in wireless networking technology has engendered a new paradigm of computing, called mobile computing, in which users carrying portable devices have access to a shared infrastructure independent of their physical locations. Wireless communication has some restraints such as disconnection, low bandwidth, a variation of available bandwidth, network heterogeneity, security risk, small storage, and low power. Power adaptation routing scheme overcome the shortage of power by adjusting the output power, was proposed. Existing power saving routing algorithm has some minor effect such as seceding from shortest path to minimize the power consumption, and number of nodes that Participate in routing than optimal because it select a next node with considering only consuming power. This paper supplements the weak point in the existing power saving routing algorithm as considering the gradual approach to final destination and the number of optimal nodes that participate in routing.

• International Journal of Computer Science & Network Security
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• v.21 no.1
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• pp.137-142
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• 2021

The Internet of Things (IoT) paradigm is at the forefront of present and future research activities. The huge amount of sensing data from IoT devices needing to be processed is increasing dramatically in volume, variety, and velocity. In response, cloud computing was involved in handling the challenges of collecting, storing, and processing jobs. The fog computing technology is a model that is used to support cloud computing by implementing pre-processing jobs close to the end-user for realizing low latency, less power consumption in the cloud side, and high scalability. However, it may be that some resources in fog computing networks are not suitable for some kind of jobs, or the number of requests increases outside capacity. So, it is more efficient to decrease sending jobs to the cloud. Hence some other fog resources are idle, and it is better to be federated rather than forwarding them to the cloud server. Obviously, this issue affects the performance of the fog environment when dealing with big data applications or applications that are sensitive to time processing. This research aims to build a fog topology job scheduling (FTJS) to schedule the incoming jobs which are generated from the IoT devices and discover all available fog nodes with their capabilities. Also, the fog topology job placement algorithm is introduced to deploy jobs into appropriate resources in the network effectively. Finally, by comparing our result with the state-of-art first come first serve (FCFS) scheduling technique, the overall execution time is reduced significantly by approximately 20%, the energy consumption in the cloud side is reduced by 18%.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.17-25
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• 2011

A convergecast is a popular routing scheme in wireless sensor networks (WSNs) in which every sensor node periodically forwards measured data along configured routing paths to a base station (BS). Prolonging lifetimes in energy-limited WSNs is an important issue because the lifetime of a WSN influences on its quality and price. Low-energy adaptive clustering hierarchy (LEACH) was the first attempt at solving this lifetime problem in convergecast WSNs, and it was followed by other solutions including power efficient gathering in sensor information systems (PEGASIS) and power efficient data gathering and aggregation protocol (PEDAP). Our solution-chain routing with even energy consumption (CREEC)-solves this problem by achieving longer average lifetimes using two strategies: i) Maximizing the fairness of energy distribution at every sensor node and ii) running a feedback mechanism that utilizes a preliminary simulation of energy consumption to save energy for depleted Sensor nodes. Simulation results confirm that CREEC outperforms all previous solutions such as LEACH, PEGASIS, PEDAP, and PEDAP-power aware (PA) with respect to the first node death and the average lifetime. CREEC performs very well at all WSN sizes, BS distances and battery capacities with an increased convergecast delay.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.4
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• pp.248-254
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• 2013

The size and power consumption of digital circuits including the dimming circuit part will increase for high-performance solid state lighting (SSL) systems in the future. This study examined the low-power consumption of adiabatic dynamic CMOS logic (ADCL) due to the principles of adiabatic charging. Furthermore, the designed low-power ADCL digital pulse width modulation (PWM) was optimized for SSL dimming systems. For this purpose, an ADCL digital 3-bit PWM was optimized in two steps. In the first step, the architecture of the ADCL digital 3-bit PWM was miniaturized. In the second step, the clock cut-off circuit was designed and added to the ADCL PWM. As a result, compared to the original configuration, 60 transistors and 15 capacitors of ADCL digital 3-bit PWM were reduced for miniaturization. Moreover, the clock cut-off circuit, which controls wake-up and sleep mode of ADCL D-FFs, was designed. The power consumption of an optimized ADCL digital PWM for all bit patterns decreased by 54 %.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.4
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• pp.1812-1824
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• 2019

The location and human activity are usually used as one of the important parameters to monitor the health status in healthcare devices. However, nearly all existing location and monitoring systems have the limitation of short-range communication and high power consumption. In this paper, we propose a new mechanism to collect and transmit monitoring information based on LoRa technology. The monitoring device with sensors can collect the real-time activity and location information and transmit them to the cloud server through LoRa gateway. The user can check all his history and current information through the specific designed mobile applications. Experiment was carried out to verify the communication, power consumption and monitoring performance of the entire system. Experimental results demonstrate that this system can collect monitoring and activity information accurately and provide the long rang coverage with low power consumption.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.6
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• pp.416-424
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• 2014

This paper presents an 8-bit pipelined analog-to-digital converter. The supply voltage applied for comparators and other sub-blocks of the ADC were 0.7V and 0.5V, respectively. This low power ADC utilizes the capacitive charge pump technique combined with a source-follower and calibration to resolve the need for the opamp. The differential charge pump technique does not require any common mode feedback circuit. The entire structure of the ADC is based on fully dynamic circuits that enable the design of a very low power ADC. The ADC was designed to operate at 1MS/s in 90nm CMOS process, where simulated results using ADS2011 show the peak SNDR and SFDR of the ADC to be 47.8 dB (7.64 ENOB) and 59 dB respectively. The ADC consumes less than 1mW for all active dynamic and digital circuitries.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.4
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• pp.462-466
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• 2010

A new buffer cache management scheme that aims at reducing power consumption in mixed HDD and NAND flash memory storage systems is presented. The proposed scheme reduces power consumption by considering different energy-consumption rate of storage devices, I/O operation type (read or write), and reference potential of cached blocks in terms of both recency and frequency. Simulation shows that the proposed scheme reduces power consumption by 18.0% on average and up to 58.9%.