• Journal of information and communication convergence engineering
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• v.5 no.1
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• pp.54-58
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• 2007

A real-time frame-layer rate control algorithm with a token bucket traffic shaper is proposed for distortion variation minimization. The proposed rate control method uses a non-iterative optimization method for low computational complexity, and performs bit allocation at the frame level to minimize the average distortion over an entire sequence as well as variations in distortion between frames. The proposed algorithm does not produce time delay from encoding, and is suitable for real-time low-complexity video encoder. Experimental results indicate that the proposed control method provides better visual and PSNR performances than the existing rate control method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.3
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• pp.1195-1211
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• 2016

The emerging video coding standard High Efficiency Video Coding (HEVC) has shown almost 40% bit-rate reduction over the state-of-the-art Advanced Video Coding (AVC) standard but at about 40% computational complexity overhead. The main reason for HEVC computational complexity is the inter prediction that accounts for 60%-70% of the whole encoding time. In this paper, we propose several fast coding unit (CU) encoding schemes based on the Merge mode and motion estimation information to reduce the computational complexity caused by the HEVC inter prediction. Firstly, an early Merge mode decision method based on motion estimation (EMD) is proposed for each CU size. Then, a Merge mode based early termination method (MET) is developed to determine the CU size at an early stage. To provide a better balance between computational complexity and coding efficiency, several fast CU encoding schemes are surveyed according to the rate-distortion-complexity characteristics of EMD and MET methods as a function of CU sizes. These fast CU encoding schemes can be seamlessly incorporated in the existing control structures of the HEVC encoder without limiting its potential parallelization and hardware acceleration. Experimental results demonstrate that the proposed schemes achieve 19%-46% computational complexity reduction over the HEVC test model reference software, HM 16.4, at a cost of 0.2%-2.4% bit-rate increases under the random access coding configuration. The respective values under the low-delay B coding configuration are 17%-43% and 0.1%-1.2%.

• Journal of the Korea Institute of Military Science and Technology
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• v.13 no.3
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• pp.405-412
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• 2010

The purpose of this paper is to compare complexity and to assess flexibility of competing transponder architectures for satellite communication services. For performance comparison, we consider three channelization techniques: digital down converter(DDC) based on the use of the cascaded integrator-comb(CIC) filter, tuneable pipeline frequency transform(T-PFT) based on the tree-structure(TS) and variable oversampled complex-modulated filter banks(OCM-FB) based on the polyphase FFT(P-FFT). The comparison begins by presenting a basic architecture of each channelization method and includes analytical expressions of the number of multiplications as a computational complexity perspective. The analytical results show that DDC with CIC filter requires the heavy computational burden and the perfect flexibility. T-PFT based on the TS provides the almost perfect flexibility with the low complexity over DDC with the CIC filter for a large number of sub-channels. OCM-FB based on the P-FFT shows the high flexibility and the best computational complexity performance compared with other approaches.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.2
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• pp.408-427
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• 2011

Intensive computational complexity is an obstacle of enabling multiview video coding for real-time applications. In this paper, we present a fast macroblock (MB) mode selection algorithm for B frames which are based on the computational complexity analyses between the MB mode selection and reference frame selection. Three strategies are proposed to reduce the coding complexity jointly. First, the temporal correlation of MB modes between current MB and its temporal corresponding MBs is utilized to reduce computational complexity in determining the optimal MB mode. Secondly, Lagrangian cost of SKIP mode is compared with that of Inter $16{\times}16$ modes to early terminate the mode selection process. Thirdly, reference frame correlation among different Inter modes is exploited to reduce the number of reference frames. Experimental results show that the proposed algorithm can promote the encoding speed by 3.71~7.22 times with 0.08dB PSNR degradation and 2.03% bitrate increase on average compared with the joint multiview video model.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.36-41
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• 2016

LDPC code has beend applied in recent communication standards, such as Wi-Fi, WiGig, 10GBased-T Ethernet as a forward error correction code. However, LDPC code is required a large amount of computational complexity due to large iterations and block lengths for high performances. To solve this problem, various research has been continously performed for reducing computational complexity. In this paper, we propose AFC algorithm to deactive the variable and check node for reduce the computational complexity.

• Journal of Computing Science and Engineering
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• v.10 no.2
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• pp.68-73
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• 2016

An efficient texture compression method is proposed based on a block matching process between the current block and the previously encoded blocks. Texture mapping is widely used to improve the quality of rendering results in real-time applications. For fast texture mapping, it is important to find an optimal trade-off between compression efficiency and computational complexity. Low-complexity methods (e.g., ETC1 and DXT1) have often been adopted in real-time rendering applications because conventional compression methods (e.g., JPEG) achieve a high compression ratio at the cost of high complexity. We propose a block matching-based compression method that can achieve a higher compression ratio than ETC1 and DXT1 while maintaining computational complexity lower than that of JPEG. Through a comparison between the proposed method and existing compression methods, we confirm our expectations on the performance of the proposed method.

• Journal of Power Electronics
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• v.18 no.1
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• pp.129-136
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• 2018

An accurate state-of-charge (SOC) estimation ensures the reliable and efficient operation of a lithium-ion battery management system. On the basis of a combined electrochemical model, this study adopts the forgetting factor least squares algorithm to identify battery parameters and eliminate the influence of test conditions. Then, it implements online SOC estimation with high accuracy and low run time by utilizing the low computational complexity of the unscented Kalman filter (UKF) and the rapid convergence of a particle filter (PF). The PF algorithm is adopted to decrease convergence time when the initial error is large; otherwise, the UKF algorithm is used to approximate the actual SOC with low computational complexity. The effect of the number of sampling particles in the PF is also evaluated. Finally, experimental results are used to verify the superiority of the combined method over other individual algorithms.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.24-30
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• 2009

This paper presents a simple resource allocation scheme for throughput enhancement in relay based orthogonal frequency division multiple access (OFDMA) cellular systems. The resource allocation schemes, which are based on the optimization problem, have high computational complexity. That is why a searching process is required on the overall allocable resources. Since these schemes should be performed in real time, we propose a simple resource allocation scheme which has very low computational complexity. Firstly, we formulate the optimization problem and draw observations for throughput maximization. Based on observations, we propose a three step allocation scheme that separates the allocable resources into three (i.e. relay, frequency and time). By doing so, the computational complexity can be reduced. Simulation results show that the proposed scheme has near-optimum performance in spite of its low computational complexity.

• ETRI Journal
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• v.39 no.3
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• pp.326-335
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• 2017

In the uplink transmission of massive (or large-scale) multi-input multi-output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low-complexity hardware architectures of Richardson iterative method-based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix-by-matrix multiplications are reformulated to matrix-vector multiplications, thus reducing the computational complexity from $O(U^2)$ to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high-mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method-based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high-mobility channel.