• Journal of Digital Contents Society
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• v.13 no.4
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• pp.491-500
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• 2012

In this paper, a new loopback BIST structure which is effective to test RF transceiver chip and LNA(Low Noise Amplifier) in the chip is presented. Because the presented BIST structure uses a baseband processor in the chip as a tester while the system is under testing mode, the developed test technique has an advantage of performing test application and test evaluation in effectiveness. The presented BIST structure can change high frequency test output signals to a low frequency signals which can make the CUT(circuits under test) tested easily. By using this technique, the necessity of RF test equipment can be mostly reduced. The test time and test cost of RF circuits can be cut down by using proposed BIST structure, and finally the total chip manufacturing costs can be reduced.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1993.10a
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• pp.239-242
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• 1993

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.713-718
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• 2016

Predicting precise specifications of differential mixed-signal circuits is a difficult problem, because analytically derived correlation between process variations and conventional specifications exhibits the limited prediction accuracy due to the phase unbalance, for most self-tests. This paper proposes an efficient prediction technique to provide accurate specifications of differential mixed-signal circuits in a system-on-chip (SoC) based on a nonlinear statistical nonlinear regression technique. A spectrally pure sinusoidal signal is applied to a differential DUT, and its output is fed into another differential DUT through a weighting circuitry in the loopback configuration. The weighting circuitry, which is employed from the previous work [3], efficiently produces different weights on the harmonics of the loopback responses, i.e., the signatures. The correlation models, which map the signatures to the conventional specifications, are built based on the statistical nonlinear regression technique, in order to predict accurate nonlinearities of individual DUTs. In production testing, once the efficient signatures are measured, and plugged into the obtained correlation models, the harmonic coefficients of DUTs are readily identified. This work provides a practical test solution to overcome the serious test issue of differential mixed-signal circuits; the low accuracy of analytically derived model is much lower by the errors from the unbalance. Hardware measurement results showed less than 1.0 dB of the prediction error, validating that this approach can be used as production test.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.612-620
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• 1987

In this paper, the optical modem for data link realization is designed with the advantages of optical fiber, large bandwidth, high speed and long haul communication. Modem interface, CCITT V.24 and EIA RS-232C is adopted for the compatibility with existing systems, and biphase coding format is used for digital modulation. And also, modem has serveral loopback test facility in order to diagnose system itself. Optical transmitter and receiver are designed to have the receiving sensitivity of -30dBm at $10^-9$BER in the short wavelength region. Developed system is capable of transmitting data rate at 1200bps up to 57.6Kbps in sync., and at any bps within DC to 200Kbps in async transmission.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.7B
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• pp.916-927
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• 2001

본 논문에서는 인터넷 환경에서 멀티미디어의 동기를 맞추어 주기 위하여 가상 클럭(VGC : Virtual Global Clock)을 구성하였고, 가상 클락 기반의 SRTS를 제안하여 미디어 내부 동기(sntra_synchronization)를 이루었다. 8bit/8kHz PCM-sampling 음성 신호에서 320byte를 한 프레임으로 했을 때 각 프레임에 순서 번호를 넣어서 미디어간의 동기(inter_synchronization)를 유지한다. Loop Back 방법을 이용하여 구성한 가상 클럭(VGC)은 통신이 가능한 모든 환경에 적용할 수 있다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1152-1157
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• 2002

In this paper, a detailed procedure of development for an AAL2 processor widely used in voice gateway application is introduced. The processor supports CPS and SSCS with voice service and framed mode data service. It provides 4 ATM virtual connections, which include 1020 AAL2 channels. The processor has one UTOPIA Level 1 interface for an ATM cell interface and 4 TDM ports for a voice channel interface. The TDM ports carry PCM/ADPCM voice streams. Most AAL2 processors are implemented as software, or hardware and software, so its latency is large. But this processor has very low latency as to CPS and SSCS because all of them are implemented in hardware. Also, it allows not only loopback and switching of CPS packets, but loopback and switching of TDM channels. The key feature is that the internal structure of the CPS and SSCS in this processor seems like as each software function, so they are called whenever they are required. In addition, they are reusable for another design and are scalable for more channels.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.13 no.8
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• pp.4123-4141
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• 2019

Autonomous driving technology is divided into 0~5 levels. Of these, Level 5 is a fully autonomous vehicle that does not require a person to drive at all. The automobile industry has been trying to develop Level 5 to satisfy safety, but commercialization has not yet been achieved. In order to commercialize autonomous unmanned vehicles, there are several problems to be solved for driving safety. To solve one of these, this paper proposes 'A Deep Learning Part-diagnosis Platform(DLPP) based on an In-vehicle On-board gateway for an Autonomous Vehicle' that diagnoses not only the parts of a vehicle and the sensors belonging to the parts, but also the influence upon other parts when a certain fault happens. The DLPP consists of an In-vehicle On-board gateway(IOG) and a Part Self-diagnosis Module(PSM). Though an existing vehicle gateway was used for the translation of messages happening in a vehicle, the IOG not only has the translation function of an existing gateway but also judges whether a fault happened in a sensor or parts by using a Loopback. The payloads which are used to judge a sensor as normal in the IOG is transferred to the PSM for self-diagnosis. The Part Self-diagnosis Module(PSM) diagnoses parts itself by using the payloads transferred from the IOG. Because the PSM is designed based on an LSTM algorithm, it diagnoses a vehicle's fault by considering the correlation between previous diagnosis result and current measured parts data.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.151-154
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• 1998

이중 전송율(5.3 과 6.3kbit/s)을 제공하는 G.723.1 음성 코더는 공중망을 통한 H.324 POTS 영상 회의 규격의 음성 코더로 채택된 것으로, MPMLQ, ACELP 알고리즘에 근거한다. 본 논문에서는 Annex A를 포함한 G.723.1 음성 코더 알고리즘을 C&S Technology에서 개발한 음성 신호 처리를 위한 범용 DSP인 CSD17C00 칩을 이용하여 실시간 응용이 가능하도록 구현하였다. G.723.1 에 대한 양방향 평가가 Codec loopback을 통해 수행되었으며, ITU에서 제공한 테스트 절차에 따라 평가되었다. 또한, 본 논문에서 구현된 G.723.1 음성 코더는 27MIPS의 계산 속도를 갖으며, 프로그램 ROM의 크기는 8.85K Words이고, 10K 데이터 ROM과 4K 데이터 RAM을 필요로 하고 있다. 경쟁 제품과의 MOS 측정 음질 평가를 실시한 결과, CSD17C00에서의 음질 성능이 더 우수함을 입증 함으로써, 본 논문에서 보여준 CSD17C00을 기반으로 구현된 G.723.1 알고리즘의 실시간 구현기술의 타당성을 검증하게 되었다.

• Proceedings of the Acoustical Society of Korea Conference
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• spring
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• pp.52-55
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• 1999

다중 전송율(16, 24, 32, 40kbps)을 제공하는 G.726 부호화기는 ADPCM (Adaptive Differential Pulse Code Modulation) 부호화법을 사용한다. 본논문에서는 G.726 ADPCM 알고리즘을 C&S Technology에서 개발한 음성 신호 처리를 위한 범용 DSP인 CSD17C00A 칩을 이용하여 실시간 응용이 가능하도록 구현하였다. G.726에 대한 양방향 평가는 Codec Loopback test을 통해 수행되었으며, W-T에서 제공한 테스트 절차에 따라 평가되었다. 본 논문에서 구현된 G.726 부호화기는 평균 11 MIPS의 계산 속도를 갖고, 프로그램 메모리 크기는 2.8K Words이고, 데이터 메모리 크기는 550 Words 를 필요로 하였다.