• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.9
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• pp.1087-1093
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• 2012

In this paper, we implemented a HF-band magnetic-field communication system consisting of an amplitude shift keying(ASK) transmitter, a pair of loop antennas, and an ASK receiver. Especially, we suggested a new ASK transmitter architecture, where a drain bias of class E amplifier is switched alternatively between two voltage levels with respect to input data. A maximum 5 W class E amplifier was designed using a low cost IRF510 power MOSFET at the frequency of 6.78 MHz. A measured sensitivity of the designed ASK receiver is -78 dBm, which consists of a log amplifier, a filter, and a comparator. Maximum communication range of magnetic-wave communication system with loop antennas was calculated using magnetic field equations in both near-field and far-field ranges. Also, in order to verify the calculated values, an indoor propagation loss was measured using a pair of loop antennas whose dimensions are $30{\times}30cm$. Maximum operating range is estimated about 35 m in case of transmitter's output power of 1 W and receiver sensitivity of -70 dBm, respectively. Finally, the communication field test using the designed ASK transmitter and receiver was successfully done at the distance of 5 m.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1120-1128
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• 2004

In this paper, we has designed and implemented Up-converter for K-band with high IMD3 performance using balanced power amplifier. It is consisted of PA module and, Local Oscillator module with reject Filter, mixer module and If block, and Up-converter has a local loop path to decide whether it operate or not and has the sensing port to inspect output power level. According to the power budget of designed Up-converter, K-band balanced power amplifier was fabricated by commercial MMIC. Measurement results of up-converter show about 40dB Gain, PldB of 29dBm and OIP3 was 38.25dBm, that is good performance compared to power budgets. We has adjusted gate voltage of MMIC to control more than 30 dB gain. This up-converter was used in transceiver for PTP and PTMP, and applied to digital communication system that use QAM and QPSK modulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.77-86
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• 2016

This paper describes a dual-mode reference-less CDR(Clock Data Recovery) operating at full / half-rate and its operation algorithm. Proposed reference-less CDR consists of a frequency detector, a phase detector, a charge pump, a loop filter, a voltage controlled oscillator, and a digital block. The frequency and phase detectors operate at both full / half-rate for dual-mode operation and especially the frequency detector is capable of detecting the difference between data rate and clock frequency in the dead zone of general frequency detectors. Dual-mode reference-less CDR with the proposed algorithm can recover the data and clock within 1.2-1.3 us and operates reliably at both full-rate (2.7 Gb/s) and half-rate (5.4 Gb/s) with 0.5-UI input jitter.

• Journal of Power Electronics
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• v.13 no.4
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• pp.516-527
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• 2013

This paper presents a new overall system for state-of-available-power (SoAP) prediction for a lithium-ion battery pack. The essential part of this method is based on an adaptive network architecture which utilizes both fuzzy model (FIS) and artificial neural network (ANN) into the framework of adaptive neuro-fuzzy inference system (ANFIS). While battery aging proceeds, the system is capable of delivering accurate power prediction not only for room temperature, but also at lower temperatures at which power prediction is most challenging. Due to design property of ANN, the network parameters are adapted on-line to the current battery states (state-of-charge (SoC), state-of-health (SoH), temperature). SoC is required as an input parameter to SoAP module and high accuracy is crucial for a reliable on-line adaptation. Therefore, a reasonable way to determine the battery state variables is proposed applying a combination of several partly different algorithms. Among other SoC boundary estimation methods, robust extended Kalman filter (REKF) for recalibration of amp hour counters was implemented. ANFIS then achieves the SoAP estimation by means of time forward voltage prognosis (TFVP) before a power pulse occurs. The trade-off between computational cost of batch-learning and accuracy during on-line adaptation was optimized resulting in a real-time system with TFVP absolute error less than 1%. The verification was performed on a software-in-the-loop test bench setup using a 53 Ah lithium-ion cell.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.3 s.333
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• pp.25-32
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• 2005

In this papers, we first, therefore, designed VCO(voltage controlled oscillator) that is composed of the dielectric resonator and the varactor diode, and then designed and fabricated PLDRO(phase locked dielectric resonator oscillator) that is combined with the sampling phase detector and loop filter. The measured results of the fabricated PLDRO at 12.05 [GHz] show the output power is 13.54 [dBm], frequency tuning range approximately +/- 7.5 [MHz], and Power variation over the tuning range less than 0.2 [dB], respectively. The phase noise which effects on bits error rate in digital communication is obtained with -114.5 [dBc/Hz] at 100 [KHz] offset from carrier, and The second harmonic suppression is less than -41.49 [dBc]. These measured results are found to be more improved than those of VCO without adopting PLL, and the phase noise and power variation performance characteristics show the better performances than those of conventional PLL.