• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2003년도 하계학술대회 논문집
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• pp.188-192
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• 2003

Pole placement method is widely used in controller design. For the stability of the closed loop system, user-specified desired locations including extra pole locations in the s-plane is chosen and by some procedure, feedback gain is obtained. In this paper, only desired pole location is used, and the calculation process is done for attaining linear quadratic stability. Similarly transformation is used for this. By computer simulations using MATLAB, the effectiveness is shown.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2001년도 춘계학술대회논문집B
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• pp.488-494
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• 2001

Many literatures, so far, have concentrated on approaches employing dependent coordinates set resulting in computational burden of constraint forces, which is needless in many cases. Some researchers developed methods to remove or calculate it efficiently. But systematic generation of the motion equation using independent coordinates set by Kane's equation is possible for any closed loop system. Independent velocity transformation method builds the smallest size of motion equation, but needs practically more complicated code implementation. In this study, dependent velocity matrix is systematically transformed into independent one using dependent-independent transformation matrix of each body group, and then motion equation free of constraint force is constructed. This method is compared with the other approach by counting the number of multiplications for car model with 15 d.o.f..

• BMB Reports
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• 제33권5호
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• pp.379-384
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• 2000

The native conformation of serpins (serine protease inhibitors) is strained. Upon cleavage of the reactive center loop of serpins by a protease, the amino terminal portion of the cleaved loop is inserted into the central ${\beta}-sheet$, A sheet, as the fourth strand, with the concomitant release of the native strain. We questioned the role of protease in this conformational switch from the strained native form into a stable relaxed state. Chemical cleavage of the reactive center loop of ${\alpha}_1-antitrypsin$, a prototype serpin, using hydroxylamine dramatically increased the stability of the serpin. A circular dichroism spectrum and peptide binding study suggests that the amino terminal portion of the reactive center loop is inserted into the A sheet in the chemically-cleaved ${\alpha}_1-antitrypsin$, as in the enzymatically-cleaved molecule. These results indicate that the structural transformation of a serpin molecule does not require interaction with a protease. The results suggest that the serpin conformational switch that occurred during the complex formation with a target protease is induced by the cleavage of the reactive center loop per se.

• 인터넷정보학회논문지
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• 제2권4호
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• pp.91-99
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• 2001

프로그램 수행시간의 대부분이 루프 구조에서 소비되고 있기 때문에 루프 구조를 가진 순차 프로그램에서 병렬성을 추출하는 연구들이 많이 행해지고 있고 그 연구들은 하나의 프로시저 내 루프 구조의 변환에 치중되고 있다. 그러나 대부분의 프로그램들은 프로시저 간 잠재된 병렬성을 가지고 있다. 본 논문에서는 프로시저 호출을 가진 루프에서 병렬성 추출 방식을 제안한다. 프로시저 호출을 포함하는 루프의 병렬화는 대부분 자료종속거리가 uniform 형태의 코드에서만 집중되었다. 본 논문에서는 자료종속거리가 uniform 코드, nonuniform 코드 그리고 복합된(complex) 코드를 가진 프로그램에서 적용 가능한 알고리즘을 제시하였으며, 제안된 알고리즘과 loop extraction, loop embedding 그리고 procedure cloning변환 방법을 CRAY-T3E로 성능 평가하였다. 성능평가 결과는 제안된 알고리즘이 효율적이라는 것을 보여준다.

• 융합신호처리학회논문지
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• 제11권2호
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• pp.169-176
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• 2010

Sag, Swell, Impulsive Transient, Harmonics 등의 비정상 전력품질 신호들은 산업체 전력전자 장비, 속도 조절 장치, 공정 제어 시스템의 운전에 상당히 나쁜 영향을 미쳐 전력 공급자 및 수용가 입장에서 매우 중요한 이슈가 되어왔다. 따라서 본 연구에서는 이상의 전력품질 신호들을 획득, 분석 및 인식하기 위하여 Matlab, Simulink, CCS 등의 소프트웨어와 TI의 TMS320C6713DSK 하드웨어 키트와 웨이블릿 변환과 신경 회로망 역전파 알고리즘을 사용하여 전력품질 인식 시스템을 구현하였다. 이 시스템의 실시간 인식 성능을 파악하기 위하여 SIL(Software In the Loop)와 PIL(Process In The Loop)를 수행하였고, 그 결과 평균 99%의 우수한 인식결과를 보여주었다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1347-1356
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• 2018

In a three-phase system, three-phase AC signals can be translated into two-phase DC signals through a coordinate transformation. Thus, the PI regulator can realize a zero steady-state error for the DC signals. In the control of a three-phase grid-connected inverter, the phase angle of grid is normally detected by a phase-locked loop (PLL) and takes part in a coordinate transformation. A novel control strategy for a three-phase grid-connected inverter with a frequency-locked loop (FLL) based on coordinate transformation is proposed in this paper. The inverter is controlled as a current supply. The grid angle, which takes part in the coordinate transformation, is replaced by a periodic linear changing angle from $-{\pi}$ to ${\pi}$. The changing angle has the same frequency but a different phase than the grid angle. The frequency of the changing angle tracks the grid frequency by the negative feedback of the reactive power, which forms a FLL. The control strategy applies to non-ideal grids and it is a lot simpler than the control strategies with a PLL that are applied to non-ideal grids. The structure of the FLL is established. The principle and advantages of the proposed control strategy are discussed. The theoretical analysis is confirmed by experimental results.

• 한국컴퓨터산업학회논문지
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• 제6권2호
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• pp.365-372
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• 2005

일반적으로 응용프로그램에서 병렬성 추출에 대한 핵심 부분은 루프이고 루프내의 첨자변수들 사이에는 자료종속성이 존재한다. 특히 문장들 사이에 가변 및 불변종속거리를 갖는 종속관계는 매우 복잡하다. 따라서 이 경우 컴파일 시 병렬성 추출은 매우 어렵다. 따라서 본 논문에서는 기존에 제시되어있는 병렬성 추출 방법들 중에서 unimodular방법과 non-unimodular방법에 대하여 분석하고 이들의 장단점을 파악하여 향후 효율적인 종속성 제거방법을 제안하는데 도움이 되고자한다.

• 전력전자학회논문지
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• 제20권2호
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• pp.152-159
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• 2015

In a weak grid condition, the precise grid impedance estimation is essential to guaranteeing the high performance current control and power transfer for a grid-connected inverter. This study proposes a precise estimation method for grid impedance by PQ variations by employing the variation method of reference currents. The operation principle of grid impedance estimation is fully presented, and the negative impact of the phase locked loop is analyzed. Estimation error by a synchronization angle in the park's transformation using the phase locked loop is derived. As a result, the variation method of reference currents for accurate estimation is introduced. The validation of the proposed method is verified through several simulation results and experiments based on a 2-kW voltage source inverter prototype.

• 한국정밀공학회지
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• 제20권4호
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• pp.103-111
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• 2003

The Denavit-Hartenberg symbolic notation provides the framework for the convenient and systematic method for the robot manipulator kinematics, but is limited its use to the lower pair mechanism or to the single loop mechanisms. The Sheth-Uicker notation is its revised and generalized version to be extended fur the entire domain of the link mechanism including the higher pairs. This paper proposes the method that uses the Sheth-Uicker notation fur the robot kinematics modeling. It uses the instantly coincident coordinate system and the closed loop chain fur the coordinate transformation. It enables us to model the velocity kinematics of the robot that has the complex structures such as the ternary links and the wheels in a systematic and rational way. As an implementation of the proposed method, the Jacobian matrices were obtained for not only the robot with two legs and a torso, but a manipulator on a mobile platform.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.