• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.76-81
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• 2013

A new phase frequency detector based digital phase-locked loop (PLL) of 125 MHz was designed using the 130 nm CMOS technology library consisting of inverting edge detectors along with a typical digital phase-locked loop to reduce the lock time and jitter for mid-frequency applications. XOR based inverting edge detectors were used to obtain a transition earlier than the reference signal to change the output more quickly. The HSPICE simulator was used in a Cadence environment for simulation. The performance of the digital phase-locked loops with the proposed phase frequency detector was compared with that of conventional phase frequency detector. The PLL with the proposed detector took $0.304{\mu}s$ to lock with a maximum jitter of approximately 0.1142 ns, whereas the conventional PLL took a minimum of $2.144{\mu}s$ to lock with a maximum jitter of approximately 0.1245 ns.

• Journal of Korean Society of Transportation
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• v.20 no.5
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• pp.163-174
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• 2002

Speeding has been reported as one of the major causes for fatal traffic accidents in Korea. The resolution against this dangerous speeding comes to make the automated speed enforcement system an enforcement tool. The speed detection device, which measures speeds of each incoming vehicles using double loop sensors, requires high accuracy. The object of this study is to develop an accurate speed measurement algorithm using double loop detectors. Some important findings are summarized as follows: 1) It was found that speed measurement errors are caused by scanning rate, distance of two loops, irregular vehicle trajectories, multiple vehicles in detection zone. 2) A proposed algorithm using two signal set proved to reduce variance as well as mean of speed measurement. 3) A proposed filtering algorithm was effective to filter irregular driving vehicles and multiple vehicles in detection zone. A comprehensive field test of developed algorithm resulted in significant improvement of speed measurement accuracy.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.108-117
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• 2003

In this paper, two types of radar vehicle detectors compatible with currently being used ILD(Inductive Loop Detector) without any modification has been developed. With these vehicle detectors based on FMCW altimeter and Doppler speedometer techniques at 24 GHz, the length and speed of a vehicle can be detected. For signal processing part, we have used DAQ board and programmed with LabView. For compatibility with traffic information network connected with existing ILD's, traffic information has been sent to VDS by using RS-232C standard interface. This development has improved approximately 10% in accuracy in terms of the speed and length information compared with that of the installed ILD in the test field.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2002.11a
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• pp.394-397
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• 2002

A design study of phase detectors for the 2.5 Gb/s CDR circuit using a standard 0.18-${\mu}{\textrm}{m}$ CMOS process has been performed. The targeted CDR is based on the phase-locked loop and thus it consists of a phase detector, a charge pump, a LPF, and a VCO. For high frequency operation of 2.5 Gb/s, phase detector and charge pump, which accurately compare phase errors to reduce clock jitter, are critical for designing a reliable CDR circuit. As a phase detector, the Hogge phase detector is selected but two transistors are added to improve the performance of the D-F/F. The charge pump was also designed to be placed indirectly input and output.

• Journal of KIISE:Software and Applications
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• v.33 no.5
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• pp.489-498
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• 2006

In this paper, we suggested a vehicle classification algorithm using pattern recognition method. At present, Inductive Loop Detector is rarely used for vehicle classification because of its low accuracy. To improve the accuracy, we suggest a new algorithm for Loop Detector using neural networks. In the developed algorithm, the inputs to the neural networks are the variation rate of frequency and occupancy-time. The output is classified vehicles. The developed algorithm was assessed at test sites and the recognition rate was 91.3percent. The results verified that the proposed algorithm improves the vehicle classification accuracy compared to the conventional method based on Loop Detector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.82-87
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• 2008

This paper presents a new fast locking dual-slope phase-locked loop. The conventional dual-slope phase-locked loop consists of two charge pumps and two phase-frequency detectors. In this paper, the dual-slope phase-locked loop was achieved with a charge pump and a phase-frequency detector as adjusting a current of the charge pump according to the phase difference. The proposed circuit was verified by HSPICE simulation with a $0.35{\mu}m$ CMOS standard process parameter. The phase locking time of the proposed dual-slope phase-locked loop was $2.2{\mu}s$ and that of the single-slope phase-locke loop was $7{\mu}s$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.3
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• pp.598-604
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• 2009

This paper proposes a vehicle detector with an anisotropic magnetoresistive (AMR) sensor and addresses experimental results to show the detector's performance. The detector consists of an AMR sensor and mechanical and electronic apparatuses. The AMR sensor, composed of four magnetoresistors, senses disturbance of the earth's magnetic field caused by a vehicle moving over the sensor and then produces an output indicative of the moving vehicle. This paper verifies performance of the detector on the basis of experimental results obtained from the field tests carried under the two traffic conditions on local highways in Korea. First, I show the vehicle counting performance on a low speed congested highway by comparing the vehicle counts measured by the detector with the exact counts. Second, both vehicle counts and average speeds calculated from the measured point-occupancy on another continuously free running highway are compared with the reference values obtained from a loop detector which has two independent loop coils, where I have used several performance indices including mean absolute percentage error (MAPE) to show the performance consistency between the two types of detectors.

• International Journal of Highway Engineering
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• v.10 no.2
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• pp.221-227
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• 2008

This study identifies the relationship between traffic data quality obtained from loop detectors and their location. Traffic data basically shows traffic flow conditions and thus, these information can be used as inputs for various transportation management strategies. Out study presents how to determine optimal downstream detector location on merging area in order to enhance the effects of ramp metering strategies. Microscopic simulation model, PARAMICS, is used as the main analytical tool. Assuming that detector location relies heavily on traffic flow characteristics in each roadway segment, we perform statistical analysis to identify homogeneous traffic conditions on merging area.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.5
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• pp.11-20
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• 2014

Due to the importance of vehicle detector which plays an essential role in generating real-life traffic information, maintaining detector data quality is preeminent in advanced traffic management and information systems (ATMIS). To this end, agencies periodically conduct performance tests on detectors. Detector evaluation is generally performed by comparing baseline data with corresponding detector data. Here, two important things need to be addressed; one is errors (or uncertainties) included in baseline data and the other is the confidence interval concept to represent evaluation results of sample data to corresponding ones of population. To resolve these problems, a new detector evaluation scheme is introduced and the scheme is applied to individual level detector evaluations of loop, video image, and radar detectors. The purpose of individual level evaluation is to eliminate the balancing (or cancelling-out) effects of over- and under-counts. As a consequence, the proposed scheme is proven to be effectively applied to real-world detector evaluations.