• Journal of Institute of Control, Robotics and Systems
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• v.4 no.2
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• pp.194-202
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• 1998

This paper describes a hardware implementation method of a Petri Net-based controller. A flexible and systematic implementation method, based on look-up tables, is suggested, which enables to build high speed Petri net-based controllers. The suggested method overcomes the inherent speed limit that arises from the microprocessors by using of matrix-based look-up tables. Based on the matrix framework, this paper suggests various specific data path structures as well as a basic data path structure, accompanied by evolution algorithms, for sub-class Petri nets. A new sub-class Petri net, named Biarced Petri Net, resolves memory explosion problem that usually comes with matrix-based look-up tables. The suggested matrix-based method based on the Biarced Petri net has as good efficiency and expendability as the list-based methods. This paper shows the usefulness of the suggested method, evaluating the size of the look-up tables and introducing an architecture of the signal processing unit of a programmable controller. The suggested implementation method is supported by an automatic design support program.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.12
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• pp.541-554
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• 1986

This paper presents the results of driving performance analysis of permanent magnet synchronous motor using a microprocessor based control system. The system consists of three phase power transistor inverters, three phase controlled rectifier, three central processing units, and sensors. The three CPUs are, respectively, used to generate PWM control signals for the inverter generating three phase sine wave, to generate the gate control signals for firing the converter, and to supervise other two CPUs. The supervisor is used to compute PI control algtorithm to three phase reference sine wave for the inverter. It is also used to maintain a constant voltage frequency ratio for the converter operating as a constant torque controller. The inverter CPU retrieves precomputed PWM patterns from look up tables because of computation speed limitations found in almost available microprocessors. The converter CPU also retrieves precomputed gate control patterns from another look-up tables. For protecting the control ststem from any damage by extraordinary over currents, the supervisor receives the data from current sensor, CT, and break down the CB to isolate the circuits from source. A resolver has a good performance characteristics of overall speed range, especially on low speed range. Therefor the speed control accuracy is impoved. The microprocessor based PM synchronous motor control system, thus, has many advantages such as constant torque characteristics, improvement of wave, limitation on extraordinary over currents, improvement of speed control accuracy, and fast response speed control using multi-CPU and look-up tables.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.276-284
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• 1999

In this paper, we propose a new technique which allows to store the pre-scaling constants directly in a table thus eliminating the cycle for computing pre-scaling constants. Especially we analyzed the range of pre-scalingconstants and rearranged them in a carry-save form using two look-up tables so that the size of the tables can be reduced significantly. The resulting scheme is compared with the previously developed method and shown to be effective with respect to area and time to implement the high-radix divider.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.330-333
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• 2021

In a CNN for image classification, a SoftMax layer is usually placed at the end. The exponentinal and logarithmic operations in the SoftMax layer are not adequate to be implemented in an accelerator circuit. The operations are usually implemented with look-up tables, and the exponential operation can be implemented in an iterative method. This paper proposes a successive approximation method to calculate a logarithm to remove a very large look-up table. By substituing the large table with two very small tables, the circuit can be reduced much. The experimental results show that the 85% area reduction can be reached with a small error degradation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.3
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• pp.391-399
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• 2023

In this paper, we presents for the first time an implementation using T-table for PIPO-64/128, 256 which are lightweight block ciphers. While our proposed implementation requires 16 T-tables, we show that the two types of T-tables are circulant and obtain variants implementations that require a smaller number of T-tables. We then discuss trade-off between the number of required T-tables (code size) and throughput by evaluating the throughput of the variant implementations on an Intel Core i7-9700K processor. The throughput-optimized versions for PIPO-64/128, 256 provide better throughput than TLU(Table-Look-Up) reference implementation by factors of 3.11 and 2.76, respectively, and bit-slice reference implementation by factors of 3.11 and 2.76, respectively.

• Journal of Multimedia Information System
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• v.5 no.2
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• pp.131-138
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• 2018

This work describes a binary image based fast Difference of Gaussian (DoG) filter using zero-dimensional (0-d) convolution and state machine look up tables (LUTs) for image and video stitching hardware platforms. The proposed approach for using binary images to obtain DoG filtering can significantly reduce the data size compared to conventional gray scale based DoG filters, yet binary images still preserve the key features of the image such as contours, edges, and corners. Furthermore, the binary image based DoG filtering can be realized with zero-dimensional convolution and state machine LUTs which eliminates the major portion of the adder and multiplier blocks that are generally used in conventional DoG filter hardware engines. This enables fast computation time along with the data size reduction which can lead to compact and low power image and video stitching hardware blocks. The proposed DoG filter using binary images has been implemented with a FPGA (Altera DE2-115), and the results have been verified.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.244-253
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• 2000

Since no single routing-switching combination performs the best under various different types of applications, a flexible network is required to support a range of polices. This paper introduces an implementation of a look-up table routing engine offering flexible routing and switching polices without performance degradation unlike those based on microprocessors. By deciding contents of look-up tables, the engine can implement wormhole routing, virtual cut-through routing, and packet switching, as well as hybrid switching, under a variety of routing algorithms. Since the routing engine has a piplelined look-up table architecture, the routing delay is as small as one flit, and thus it can overlap multiple routing actions without performance degradation in comparison with hardwired routers dedicated to a specific policy. Because four pipeline stages do not induce a hazard, expensive forwarding logic is not required. The routing engine can accommodate four physical links with a time shared cut-through bus or single link with a cross-bar switch. It is implemented using Xilinx 4000 series FPGA.

• Nuclear Engineering and Technology
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• v.47 no.4
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• pp.407-415
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• 2015

A developing post-dryout region is characterized by significant heat transfer enhancements compared with the fully developed post-dryout region. The heat transfer enhancements are mainly due to upstream disturbance and entrained droplets in the region immediately downstream of the critical heat flux location. In this paper, an improved heat transfer correlation is developed for the developing post-dryout regions in vertical tubes over a wide range of flow conditions. The correlation represents a correction factor for the fully developed film-boiling look-up table to be applied to the developing post-dryout region. The new correlation significantly improves the heat transfer prediction in the developing post-dryout regions and provides very good agreement with the experimental data.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.29B no.9
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• pp.76-87
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• 1992

A novel self-organizing fuzzy plus PD control algorithm is proposed, where the proposed controller consists of a typical fuzzy reasoning part and self organizing part in which both on-line and off-line algorithms are employed to modify the Look-Up Table(LUT) for the fuzzy control rules and to decide how much fuzzy rules are to be modifid after evaluating the control performance, respectively. And the fuzzy controller is replaced by a PD controller in a prespecified region nearby the set point for good settling actions, where gain parameters are determined by fuzzy rules based on the magnitude of error velocity at the instant when the output penetrates into the prespecified region. To show the effectiveness of the proposed controller, extensive computer simulation results as well as experimental results are illustrated for an inverted pendulum system.