Hardware implementation of Petri net-based controller with matrix-based look-up tables

행렬구조 메모리 참조표를 사용한 페트리네트 제어기의 하드웨어 구현

  • 장래혁 (서울대학교 컴퓨터공학과) ;
  • 정승권 (서울대학교 전기공학부) ;
  • 권욱현 (서울대학교 전기공학부)
  • Published : 1998.04.01

Abstract

This paper describes a hardware implementation method of a Petri Net-based controller. A flexible and systematic implementation method, based on look-up tables, is suggested, which enables to build high speed Petri net-based controllers. The suggested method overcomes the inherent speed limit that arises from the microprocessors by using of matrix-based look-up tables. Based on the matrix framework, this paper suggests various specific data path structures as well as a basic data path structure, accompanied by evolution algorithms, for sub-class Petri nets. A new sub-class Petri net, named Biarced Petri Net, resolves memory explosion problem that usually comes with matrix-based look-up tables. The suggested matrix-based method based on the Biarced Petri net has as good efficiency and expendability as the list-based methods. This paper shows the usefulness of the suggested method, evaluating the size of the look-up tables and introducing an architecture of the signal processing unit of a programmable controller. The suggested implementation method is supported by an automatic design support program.

Keywords

References

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