• 한국산업정보학회논문지
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• 제23권3호
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• pp.117-129
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• 2018

This study examines the impact of severe weather on lean supply chains. First, this paper reviewed the literature on the disruptions and damages that severe weather events cause on supply chain. Then, several recent examples of lean supply chain disruptions due to severe weather were discussed. The results of the study indicated that the frequency of weather related disasters is increasing and extreme weather events will increase potential risks to supply chains. First, building organizational resilience will help firms look beyond efficiency and profits in managing lean supply chains. Second, the concept of sole sourcing may need rethinking to maintain a supply chain that is lean and resilient. Third, organizations must plan ahead for supply chains in unpredictable weather. Fifth, communication is a key for anticipating and avoiding the impact of severe weather. This study proposes of a set of strategies, both theoretical and practical, that business firms should develop to effectively prevent and respond to severe weather related disruptions in lean supply chains.

• 한국경영과학회지
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• 제30권3호
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• pp.67-80
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• 2005

This paper deals with a container terminal where containers are discharged by quay cranes from a ship and transported by a fleet of vehicles to the terminal yard. Since container terminals are fully utilized in general, It is important to increase terminal throughput by discharging the containers out of the ship without any delay, At the operational level, it should be decided which vehicle transports which container. The vehicle dispatching decision should be carefully made since the container discharging time increases when the quay cranes wait idle for the vehicles. This paper presents vehicle dispatching heuristics with the objective of minimizing the total container discharging time. The heuristics are based on a network flow model and a look-ahead concept. Through some experiments, the performance of the dispatching methods is evaluated.

• 경영과학
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• 제12권2호
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• pp.43-62
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• 1995

For a complex scheduling system like time table construction, its optimal solution, if exists, is hard to obtain. In this paper, the scheduling environment is reasonably confined as where objects have their own events competing for better slots on boards, and objects have their own board slot preferences and belong to one or more classes of the society which globally constrains them. Here, two phase method is suggested, where the first phase is human-like preference driven and the second phase is for fine tuning by considering all the factors given. Designed and implemented in our system HI-SCHED are dynamic object switching, temporal-constraint-driven intelligent backtracking, case-based revisions, object-based approach, and so on. Some satisfaction degrees are also defined to measure the usefulness of our method. In addition, look-ahead dynamic object switching is considered, and additional global constraints are introduced and processed. A simple scheme is also used to verify the usefulness of the post processing scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.778-780
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• 2000

The 74181 is arithmetic logic units(ALU)/function generator. This circuit performs 16 binary arithmetic operations on two 4-bit words. And a full carry look-ahead scheme is made available in this device. The 74181 can also be utilized as a comparator. This circuit has been also designed to provide 16 possible functions of two Boolean variables without the use of external circuitry. This paper analyzes the function of the logic and the implementation adopted in the design of 74181. The understanding of the logic characteristics of this chip enables us to improve future applications.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 A
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• pp.3-6
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• 2000

In this paper the concept of voltage stability operating limit in optimal power flow problem is described. A methodology of optimal power flow considering voltage stability margin is proposed based on auxiliary constraint to get a secure dispatch solution. The look-ahead margin is used to shift dispatch solutions to the secure direction in proposed framework. The a1gorithm proposed is successfully tested on IEEE 30-bus system.

• 한국항만경제학회:학술대회논문집
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• 한국항만경제학회 2007년도 정책세미나 및 국제학술대회
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• pp.291-312
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• 2007

This paper is designed to look for a specialized strategies by drawing the special features of Busan New Port from both a comparative analysis of major factors of harbor competitiveness and a SWOT analysis of Yangshan Port, one of the biggest competitive ports in Northeast Asia, so that Busan New Port may preoccupy a status as the hub port of the area. The researcher would like to suggest the following measures to make Busan New Port serve as the central port of Northeast Asia on the basis of the findings; Korea should push ahead with creating a railroad transportation linking with Eurasia Contient, secure the amount of goods and resources with the help of the early development of the surrounding complex of the port, make a considerable progress in the level of port service, come up with a differentiation strategies for harbor marketing activities and improve its productivity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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• pp.462-466
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• 1989

This paper describes the methods of spline low-order polynomial trajectory planning using only a few limited look-ahead knots on the desired trajectory for the real-time computing. Specifically presented are the mixed joint trajectory planning methods which apply linear or LSPB method to initial and finial segments, overlapped cubic spline method to the other segments, where the displacements for initial and finial segments are chosen to be relatively smaller than the displacements for the other, equidistant segments. Experimental and simulation results of these methods show smooth motions and improved path tracking performances compared with any other interpolated joint trajectory planning methods.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.165-168
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• 2001

This paper presents a design of a divide unit supporting IEEE-754 floating point standard single-precision with 32-bit word length. Its functions have been verified with ALTERA MAX PLUS II tool. For a high-speed division operation, the radix-4 non-restoring algorithm has been applied and CLA(carry-look -ahead) adders has been used in order to improve the area efficiency and the speed of performance for the fraction division part. The prevention of the speed decrement of operations due to clocking has been achieved by taking advantage of combinational logic. A quotient select block which is very complicated and significant in the high-radix part was designed by using P-D plot in order to select the fast and accurate quotient. Also, we designed all division steps with Gate-level which visualize the operations and delay time.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.967-970
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• 2003

A new adder-and-accumulator (A$^2$C) adapted to pipelined Δ$\Sigma$ modulators is proposed in this paper. With the viewpoint of area consumption, registers are removed in the existing pipelined Δ$\Sigma$ modulator, and then adder and accumulator are merged. In order to optimize area consumption, speed and power consumption, dynamic carry look-ahead adder (CLA) is adopted in $A^2$C. Moreover, a guideline for the transistor sizing in CLA with regard to the minimization of the energy-delay-area product (EDAP) is proposed[1]. The proposed $A^2$C has been verified by HSPICE simulations.

• ETRI Journal
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• 제31권4호
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• pp.393-398
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• 2009

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.