• Title/Summary/Keyword: Logical circuit

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The Effects of Mental Capacity and Size of Chunk of Problem Solver and Mental Demand of Problem on Science Problem Solving

  • Ahn, Soo-Young
    • Journal of The Korean Association For Science Education
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    • v.22 no.5
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    • pp.1030-1043
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    • 2002
  • The development of cognitive psychology provides us a theoretical base from which we can obtain information about human problem solving. One purpose of this study was to investigate the effects of cognitive psychological factors on the problem solving of the two kinds of tasks (content free, content specific). And the other purpose was to find out the existence of critical situation in problem solving process. Even the items of tasks with the same logical structure and content knowledge could have different sizes of mental demand. The results were as follows. The mental demand of the problem, and the problem solver's mental capacity, might be the main factors in problem solving. Critical situation of both a group and an individual existed in the tasks that need content free knowledge (FIT 752 task). But the critical situation of a group was completely different from that of the individual in the tasks that need content specific knowledge (electric circuit task). According to the analysis of achievement for each individual in the task that need content specific knowledge, the critical situation of an individual existed in problem solving, but the critical situation of a group was not existed by were summed up the individual results.

A Study about Preventing Improper Working of Equipment on ATS System by Signaling Equipment (신호장치에 의한 ATS 신호장치 오동작 방지에 대한 연구)

  • Ko, Young-Hwan;Choi, Kyu-Hyoung
    • Proceedings of the KSR Conference
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    • 2008.06a
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    • pp.579-587
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    • 2008
  • Promotion of the line no.2 in Seoul Metro was changing from the existing signaling facilities for ATS(Automatic Train Stop) vehicles to the up-to-date signaling facilities for ATO(Automatic Train Operation). But, in consequence of conducting a trial run after being equipped with the ATO signaling facilities, the matter related to mix-operation with the existing ATS signaling facilities appeared. The operation of the existing ATS signaling system in combination with the ATO signaling system has made improper working related to frequency recognition of the ATS On-board Computerized Equipment. This obstructs operation of a working ATS vehicle. That is, as barring operation of an ATS vehicle that should proceed, it may make the proceeding ATS vehicle stop suddenly and after all, it will cause safety concerns. In this paper, we designed a wayside track occupancy detector that previously prevents improper working related to frequency recognition of the ATS On-board Computerized Equipment by gripping classification and working processes of operating trains throughout transmission of local signaling information from the existing facilities, which does not need to change or replace the existing signaling facilities. Furthermore, we described general characteristics of the wayside track occupancy detector and modeled the IFC(InterFace Contrivance) device and the logical circuit recognizing signal information. Then, we made an application program of PLC(programmable Logic Computer) based on the stated model. We, in relation to data transfer method, used the frame in TCP/IP transfer mode as the standard, and we demonstrated that ATO transmission frequency is intercepted.

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A CPLD Low Power Algorithm considering the Structure (구조를 고려한 CPLD 저전력 알고리즘)

  • Kim, Jae Jin
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.10 no.1
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    • pp.1-6
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    • 2014
  • In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

An Efficient Boolean Query Processing in Information Retrieval (효율적인 부울 질의 연산에 관한 연구)

  • 채승기;남영광;박현주
    • Journal of the Korean Society for information Management
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    • v.13 no.1
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    • pp.173-185
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    • 1996
  • In this paper, we propose four optimizing methods for effectively processing queries in the Booleam information retrieval system ; (i) the short-circuit evaluation scheme used for optimizing logical expressions in programming lan-guages is applied to Boolean queries.(II) use the difference of the number of index word frequencies appearing in the related documents. (IIi) reduce the number of operators in the queries by applying the distribution law in the set theory. (iv) evaluate only once for the repeated expressions in the query. These methods have been implemented and tested in KRISTAL-II system on the UNIX workstation environment.

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A Study on developing the Battery Management System for Electric Vehicle (전기자동차용 배터리 관리 시스템에 관한 연구)

  • Han, A-Gun;Park, Jae-Hyeon;Choo, Yeon-Gyu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.882-883
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    • 2013
  • With the development of the society, pure electric vehicles will be surely important of the future. Electric vehicle requires various technology like motor driving, battery management, operational efficiencies and so on. Battery management is indeed the most important to enhance battery's performance and life. This paper has deeply discussed and studied on the lithium-polymer battery management system of pure electric vehicle. First of all we have analyzed the characteristic of the lithium-polymer batteries and the factors influenced on the state of charge. Then a logical SOC measuring method has been raised, which is the combination of open circuit voltage and Ah integration. The next we will introduce the design of battery management system, the battery management system performs many functions, such as inspecting the whole process, when it's running cell equalization protecting and diagnosing the battery, estimating the state of charge. The module design style including microcontroller, data aquisition module, charging control module and serial communication module. To arrive at conclusions, the battery management system which this paper has introduced is reliable and economical.

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Global Redundancey Check by VLSI Test Theory (VLSI 테스트 이론을 이용한 Global Redundancy 조사)

  • Lee, Seong-Bong;Chong, Jong-Wha
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.26 no.4
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    • pp.138-144
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    • 1989
  • In this paper, a new method is proposed to remove the logical redundancy for the gate-level circuit optimization. In this method, only the fanout-branch signals in the circuits, not all the signals, are examined for redundancy. When a signal is determined to be nonredundant, other nonredundant signals are found out by the efficient procedure, using only the informations which are generated in the course of the redundancy-check. In order to avoid the re-examination of a signal for redudancy, a heuristic method is proposed to determine the redundancy-checking order of signals. The proposed method is heuristic, based on the VLSI test theory. It is much faster than other methods, since it does not reexamine a signal for redundancy.

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The Methods and Its Application of Long Distance Trail Planning in a Mountainous Region (산악지역에서의 장거리 트레일 조성 계획방법 및 적용)

  • Hwang, Guk-Woong;Jang, Byoung-Kwan
    • Journal of Korean Society of Rural Planning
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    • v.17 no.3
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    • pp.55-65
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    • 2011
  • Long distance trail or trail system planning is the first important step in transforming your vision into reality. Planning presents a vision for a trail or trail system and brings a comprehensive, long-range perspective. The master plan provides solid, credible recommendations for developing a trail or trail system that is safe, convenient, well used, supported by local residents, practicality to implement, and customized to meet the needs of the community, you will need to follow a logical planning. The key elements of master planning includes site assessment, vision, goals and objectives, routing and design, implementation strategies. Trails or trail systems should provide linkages to popular destinations, safely accommodate a variety of users, and be sensitive to any negative impacts on the natural environment and wildlife. Trails planners also need to think about how the trail, or trail system will function in the future as areas are developed or trail population increases. All of these factors during the planning process will ensure the existence of high-quality facilities for years to come. Project for Nakdong-jungmaek trail planning combine long distance trail with circuit way. That project is a planning brought out the best in each of Tokai natural way and Cotswold way. That is planning which is combined a wooded trail in Tokai natural way with access and facilities improving economy in Cotswold way. Also That planning embraces a core cultural center which is concerned forest or wood to come more people.

Parallel Architecture Design of H.264/AVC CAVLC for UD Video Realtime Processing (UD(Ultra Definition) 동영상 실시간 처리를 위한 H.264/AVC CAVLC 병렬 아키텍처 설계)

  • Ko, Byung Soo;Kong, Jin-Hyeung
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.5
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    • pp.112-120
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    • 2013
  • In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.

Intermediate-Representation Translation Techniques to Improve Vulnerability Analysis Efficiency for Binary Files in Embedded Devices (임베디드 기기 바이너리 취약점 분석 효율성 제고를 위한 중간어 변환 기술)

  • Jeoung, Byeoung Ho;Kim, Yong Hyuk;Bae, Sung il;Im, Eul Gyu
    • Smart Media Journal
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    • v.7 no.1
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    • pp.37-44
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    • 2018
  • Utilizing sequence control and numerical computing, embedded devices are used in a variety of automated systems, including those at industrial sites, in accordance with their control program. Since embedded devices are used as a control system in corporate industrial complexes, nuclear power plants and public transport infrastructure nowadays, deliberate attacks on them can cause significant economic and social damages. Most attacks aimed at embedded devices are data-coded, code-modulated, and control-programmed. The control programs for industry-automated embedded devices are designed to represent circuit structures, unlike common programming languages, and most industrial automation control programs are designed with a graphical language, LAD, which is difficult to process static analysis. Because of these characteristics, the vulnerability analysis and security related studies for industry automation control programs have only progressed up to the formal verification, real-time monitoring levels. Furthermore, the static analysis of industrial automation control programs, which can detect vulnerabilities in advance and prepare for attacks, stays poorly researched. Therefore, this study suggests a method to present a discussion on an industry automation control program designed to represent the circuit structure to increase the efficiency of static analysis of embedded industrial automation programs. It also proposes a medium term translation technology exploiting LLVM IR to comprehensively analyze the industrial automation control programs of various manufacturers. By using LLVM IR, it is possible to perform integrated analysis on dynamic analysis. In this study, a prototype program that converts to a logical expression type of medium language was developed with regards to the S company's control program in order to verify our method.

Wire Recognition on the Chip Photo based on Histogram (칩 사진 상의 와이어 인식 방법)

  • Jhang, Kyoungson
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.111-120
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    • 2016
  • Wire recognition is one of the important tasks in chip reverse engineering since connectivity comes from wires. Recognized wires are used to recover logical or functional representation of the corresponding circuit. Though manual recognition provides accurate results, it becomes impossible, as the number of wires is more than hundreds of thousands. Wires on a chip usually have specific intensity or color characteristics since they are made of specific materials. This paper proposes two stage wire recognition scheme; image binarization and then the process of determining whether regions in binary image are wires or not. We employ existing techniques for two processes. Since the second process requires the characteristics of wires, the users needs to select the typical wire region in the given image. The histogram characteristic of the selected region is used in calculating histogram similarity between the typical wire region and the other regions. The first experiment is to select the most appropriate binarization scheme for the second process. The second experiment on the second process compares three proposed methods employing histogram similarity of grayscale or HSV color since there have not been proposed any wire recognition method comparable by experiment. The best method shows more than 98% of true positive rate for 25 test examples.