• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1535-1538
• /
• 2002

The flexibility of content addressable mem-ory (CAM) can greatly be extended through the use of trits (ternary digits) Trits consist of binary logical values “0” and “1” with addition of “x” (“dont’t care”). The “dont’t care“is extremely useful for providing com- pact representation of sets of bit strings. In this paper, we propose a new ternary CAM with Hamming distance search functions. Each memory cell in the CAM consists of a pair of lambda diodes which can store trits, namely, a logical “0”, “1” and “x” (“dont’t care“). The CAM can compare stored data and an input data in parallel, and find stored data with Hamming distance within a certain range (“near match“). Also, the interrogation characteristics of the ternary CAM are analyzed in detail. Furthermore, the results obtained these analyses are fully confirmed by simulation using the circuit analysis program HSPICE.

• Proceedings of the KIEE Conference
• /
• 2002.11d
• /
• pp.197-199
• /
• 2002

The invention of VHDL(Very High Speed Integrated Circuit Hardware Description Language), Technical language of Hardware, is a kind of turning point in digital circuit designing, which is being more and more complicated and integrated. Because of its excellency in expression ability of hardware, VHDL is not only used in designing Hardware but also in simulation for verification, and in exchange and conservation, composition of the data of designs, and in many other ways. Especially, It is very important that VHDL is a Technical language of Hardware standardized by IEEE, intenational body with an authority. The biggest problem in modern circuit designing can be pointed out in two way. One is a problem how to process the rapidly being complicated circuit complexity. The other is minimizing the period of designing and manufacturing to survive in a cutthroat competition. To promote the use of VHDL, more than a simple use of simulation by VHDL, it is requested to use VHDL in composing logical circuit with chip manufacturing. And, by developing the quality of designing technique, it can contribute for development in domestic industry related to ASIC designing. In this paper in designing SMPS(Switching mode power supply), programming PWM by VHDL, it can print static voltage by the variable load, connect computer to chip with byteblaster, and download in Max(EPM7064SLCS4 - 5)chip of ALTER. To achieve this, it is supposed to use VHDL in modeling, simulating, compositing logic and product of the FPGA chip. Despite its limit in size and operating speed caused by the specific property of FPGA chip, it can be said that this method should be introduced more aggressively because of its prompt realization after designing.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.11
• /
• pp.35-43
• /
• 2008

A new effective parallel decoding method has been developed for context-based adaptive variable length codes. In this paper, several new design ideas have been devised for scalable parallel processing, less area, and less power. First, simplified logical operations instead of memory look-ups are used for fast low power operations. Second the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of input are simultaneously analyzed. For comparison, we have designed the logical operation based parallel decoder for M=8 and a typical conventional method based decoder. High speed parallel decoding is possible with our method. For similar decoding rates (1.57codes/cycle for M=8), our new approach uses 46% less area than the typical conventional method.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.8
• /
• pp.2528-2535
• /
• 2000

Technology mapping is a part of VLSI CAD system, where circuits in logical level are mapped into circuits in physical level. The performance of technology mapping system is evaluatecJ by the delay and area of the resulting circuits. In the sequential circuits, the delay of the circuit is decided by the maximal delay between registers. In this work, we introduce an FPGA mapping algorithm improved by retiming technique used in constructive level and iterative level, and by fuzzy logic technique. Initial circuit is mapped into an FPGA circuit by constructive manner and improved by iterative retiming. Criteria given to the initial circuit are structured hierarchically by decision-making functions of fuzzy logic. The proposed system shows better results than previous systems by the experiments with MCNC benchmarkers.

• Journal of Institute of Control, Robotics and Systems
• /
• v.2 no.4
• /
• pp.337-343
• /
• 1996

In this paper, we investigate the defect detection by making use of pre-made reference image data and classify the defects by using the artificial neural network. The approach is composed of three main parts. The first step consists of a proper generation of two reference image data by using a low level morphological technique. The second step proceeds by performing three times logical bit operations between two ready-made reference images and just captured image to be tested. This results in defects image only. In the third step, by extracting four features from each detected defect, followed by assigning them into the input nodes of an already trained artificial neural network we can obtain a defect class corresponding to the features. All of the image data are formed in a bit level for the reduction of data size as well as time saving. Experimental results show that proposed algorithms are found to be effective for flexible defect detection, robust classification, and high speed process by adopting a simple logic operation.

• ETRI Journal
• /
• v.26 no.6
• /
• pp.513-519
• /
• 2004

This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a $0.35{\mu}m$ CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.18 no.1
• /
• pp.25-34
• /
• 1981

Any logical stuckft faults in multivalued combinational circuits are analyzed using the concept of Boolean difference. The algebra employed is the implementation oriented algebra developed by Allen and Givone. All the lines in the circuit are classified into five types according to their properties. For each type, the equation that represents the complete test set is derived and proved. All the results in examples are confumed to be correct by comparing the truth tables of the normal and faulty circuits.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.2273-2274
• /
• 2008

It respects the high speed of the Bitter expense decoder from the present paper ACS (Add Compare Select) block structures of new method it proposed. It became component anger of existing and it substituted it added all input price it predicted with the method which reduces the operation which is unnecessary it chose respectively ACS unit and a union logical operation circuit and the result after operation one in advance.

• 한국정보교육학회:학술대회논문집
• /
• 2006.08a
• /
• pp.109-115
• /
• 2006

오늘날 IT의 급속한 진보는 사회적, 경제적 변화를 가져왔다. 그리고 많은 나라들이 정보화시대에 선두를 차지하려 노력하고 있다. 이에 미래의 IT산업을 선도할 인재들의 첫 출발점이라고 할 수 있는 초등학교에서의 정보영재교육의 필요성이 더욱 중요시되고 있으며, 현대 디지털 사회 전 분야에 걸쳐 없어서는 안 될 필수적인 요소로 사용되고 있는 디지털 시스템의 동작 원리를 이해하는 것이 요구되고 있다. 이에 디지털 시스템의 동작 원리를 이해하는 데 기초가 되는 디지털 논리 회로에 대한 내용을 초등학교 아동들이 쉽고 흥미롭게 이해할 수 있는 교육방법을 개발하여 실생활에서 필요한 디지털 시스템을 창의적으로 설계하고, 이를 통한 문제해결능력을 향상하고자 한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.8 no.1
• /
• pp.30-37
• /
• 1983

In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.