대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 2008년도 제39회 하계학술대회
- /
- Pages.2273-2274
- /
- 2008
고속 비터비 디코더를 위한 효율적인 ACS 설계
Efficient ACS Design for High Speed Viterbi Decoder
- Lee, Seul-Ki (School of Information&Communication Engineering, Sungkyunkwan University) ;
-
Kim, In-Soo
(School of Information&Communication Engineering, Sungkyunkwan University) ;
-
Min, Hyoung-Bok
(School of Information&Communication Engineering, Sungkyunkwan University) ;
- Ryu, Joong-Kyung (Division of Computer Science and Information, Daelim College)
- 발행 : 2008.07.16
초록
It respects the high speed of the Bitter expense decoder from the present paper ACS (Add Compare Select) block structures of new method it proposed. It became component anger of existing and it substituted it added all input price it predicted with the method which reduces the operation which is unnecessary it chose respectively ACS unit and a union logical operation circuit and the result after operation one in advance.
키워드