• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.15-24
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• 1998

This paper proposes a new template matching algorithm and its chip design. The CC and SAD algorithms require the massive amount of computation. Hence, several algorithms using quantization schemes have been proposed to reduce the amount of computation and its hardware cost. the proposed algorithm called the EMPPM improves at least 22% of the noise margin compared with the MPPM algorithm. In addition, the proposed architecture can reduce the gate count by more than 60% of that used in the SAD algorithm without usig quantization schemes and 28% of the MPPM algorithm. The VHDL models have been simulated by using the CADANCETEX>$^{TM}$ and logic synthesis has been performed by using the SYNOPSYSTEX>$^{TM}$ with $0.6\mu\textrm{m}$ SOG(sea-of-gate) cell library. The implemented chip consists of 35,829 gates, operates at 100 MHz (worst case 53 MHz) and performs the template maching with the speed of 200 Mpixels/sec.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.10a
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• pp.125-130
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• 1999

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2000.04a
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• pp.165-170
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• 2000

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, in the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierachical control structure consisting of basic level and high level that modify control rules.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.5
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• pp.259-267
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• 2001

칩의 집적도에 비례하여 설계검증 및 칩 제작 후의 결함점검은 갈수록 어려워지며 이러한 테스트 문제의 원초적 해결을 위하여 다양한 테스트설계 기술이 널리 개발되고 있다. 상위 수준의 테스트설계에서는 회로의 기능에 대해서는 알 수 있으나 구조에 대해서는 알 수 없고, 하위 수준의 테스트설계에서는 회로의 구조를 알 수 있으나 기능은 알 수 없다. 따라서 테스트 설계는 기능을 기술하는 상위 수준에서부터 고려되어 하위 게이트수준에서 스캔플립플롭을 선택하여야 최적화된 성능을 얻을 수 있다. 본 논문에서는 테스트용이도를 증진시키기 위해, 상위수준의 기능정보에 대해서는 테스트점을 삽입하여 제어흐름(control flow)을 변경하고, 상위 수준의 합성 후에 하위 수준에서 스캔플립플롭을 선택하여 다시 합성하는 상위.하위 수준에서 통합된 테스트 합성 기술을 제안한다. 실험결과 통합된 테스트 합성 기술이 대부분의 벤치마크 회로에서 높은 고장검출율을 보여주고 있다.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.5 no.2
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• pp.108-113
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• 2005

This paper suggests a control method for an efficient topology/parameter evolution in a bond graph-based GP design framework that automatically synthesizes designs for multi-domain, lumped parameter dynamic systems. We adopt a hierarchical breeding control mechanism with fitness-level-dependent differences to obtain better balancing of topology/parameter search - biased toward topological changes at low fitness levels, and toward parameter changes at high fitness levels. As a testbed for this approach in bond graph synthesis, an eigenvalue assignment problem, which is to find bond graph models exhibiting minimal distance errors from target sets of eigenvalues, was tested and showed improved performance for various sets of eigenvalues.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.9
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• pp.761-773
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• 1991

In this paper, an algorithm for automatic schematic generation which creates schematic diagram from netlist are proposed. The important objectives on schematic generation are readability and clarity of resulting schematics. Each stage of generation should aim at enhancing these objectives. For this reason, schematic generation problem is divided into 5 subproblems` preprocessing, logical placement, pin assignment and improvement of placement, global routing, and detailed routing. The algorithm is implemented in C language, and it generates schematics from the results of logic synthesis in order to make it east for designers to understand the design and reflect their knowledge into design.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.12-18
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• 1997

An efficient synthesis method of cellular architecture FPgA is proposed in this paper. To generate a logical representation called complex term which is to be directly mapped onto the cellular architecture FPGA, and SO or ESOP minimization tool was used in previous methods. Instead, we use a logic function transformed into BDD (binary decision diagram) in the actual generation of the complex temrs. In this process it estimates the cost(i.e. the number of complex terms) for three branches, 0-branch and 1-branches. This process is continued over the whole BDD to do such computation, and we observed that the number of complex terms has been reduced compared to the previous results.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.11
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• pp.132-139
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• 1993

This paper presents a new performance-driven multi-levelizer which transforms a two-level description into a boolean network of the multilevel structure satisfied with user's costraints, such as chip area, the number of wires and literals, maximum delay, function level, fanin, fanout, etc.. The performance of circuits is estimated by reference to the informations in cell library through the cell mapping phase, and multi-levelization of circuits is constructed by the decomposition using the kernel and factoring concepts. Here, the saving cost of a common subexpression is defined to the sum of area and delay saved, when it is substituted. The experiments with MCNC benchmarks show the efficiency of the proposed method.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 1999.05a
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• pp.193-198
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• 1999

In this paper, it is presented a new technique to the design and real-time implementation of fuzzy control system based-on digital signal processors in order to improve the precision and robustness for system of industrial robot. Fuzzy control has emerged as one of the most active and fruitful areas for research in the applications of fuzzy set theory, especially in the real of industrial processes. In this thesis, a self-organizing fuzzy controller for the industrial robot manipulator with a actuator located at the base is studied. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variable of the controller, In the synthesis of a FLC, one of the most difficult problems is the determination of linguistic control rules from the human operators. To overcome this difficult, SOFC is proposed for a hierarchical control structure consisting of basic level and high level that modify control rules.