• Title/Summary/Keyword: Logic size

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A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme

  • Yamauchi, Hiroyuki
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.2
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    • pp.118-129
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    • 2010
  • A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

Scatternet Formation Algorithm based on Relative Neighborhood Graph

  • Cho, Chung-Ho;Son, Dong-Cheul;Kim, Chang-Suk
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.8 no.2
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    • pp.132-139
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    • 2008
  • This paper proposes a scatternet topology formation, self-healing, and self-routing path optimization algorithm based on Relative Neighborhood Graph. The performance of the algorithm using ns-2 and extensible Bluetooth simulator called blueware shows that even though RNG-FHR does not have superior performance, it is simpler and easier to implement in deploying the Ad-Hoc network in the distributed dynamic environments due to the exchange of fewer messages and the only dependency on local information. We realize that our proposed algorithm is more practicable in a reasonable size network than in a large scale.

Implementation of a Thermal Control System using RVEGA - Optimal Fuzzy Controller (RVEGA - 최적 퍼지 제어기를 이용한 온도 제어 시스템의 구현)

  • Kim, Jung-Soo;Jeong, Jong-Won;Song, Ho-Shin;Kim, Tae-Woo;;Lee, Joon-Tark
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2099-2101
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    • 2001
  • In general, the thermal control system has nonlinearity and the time delay, futhermore, it is difficult to design the free size controller, because the external environmental disturbances, such as rapid temperature change. Many researchers in this field are preferring to adapt the fuzzy logic control methods. But it is noted that the actuator identification of M.F.'s used in FLC is very difficult. Therefore in this paper, an implementation technique of thermal control system using RVEGA based optimal fuzzy control was proposed. It's superiority and exaction in controller design processes hardware in implementation were proved through a series of simulations and experimentations.

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Fuzzy Modeling Using Fuzzy Equalization and GA (퍼지 균등화와 유전알고리즘을 이용한 퍼지 모델링)

  • Kim, S.S.;Go, H.J.;Jun, B.S.;Ryu, J.W.
    • Proceedings of the KIEE Conference
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    • 2001.07d
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    • pp.2653-2655
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    • 2001
  • In this paper, we proposed a method of modeling a system using Fuzzy Equalization(FE) and Genetic Algorithm(GA). The initial model is constructed using FE. The antecedent parameters and the rules in fuzzy logic are tuned by GA. The proposed system minimizes the modeling error and the size of structure. The process of building membership functions using PDF(Probability Density Function) and GA tunes the antecedent parameter and rules for minimizing the error and structure. The usefulness of proposed method is demonstrated by applying to Box-Jenkins furnace data.

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Design of a Key Scheduler for Supporting the Parallel Encryption and Decryption Processes of HIGHT (HIGHT 암복호화 병렬 실행을 위한 Key Scheduler 설계)

  • Choi, Won-Jung;Lee, Je-Hoon
    • Journal of Sensor Science and Technology
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    • v.24 no.2
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    • pp.107-112
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    • 2015
  • HIGHT is an 64-bit block cipher, which is suitable for low power and ultra-light implementation that are used in the network that needs the consideration of security aspects. This paper presents a parallel key scheduler that generates the whitening keys and subkeys simultaneously for both encryption and decryption processes. We construct the reverse LFSR and key generation blocks to generate the keys for decryption process. Then, the new key scheduler is made by sharing the common logics for encryption and decryption processes to minimize the increase in hardware complexity. From the simulation results, the logic size is increased 1.31 times compared to the conventional HIGHT. However, the performance of HIGHT including the proposed key scheduler can be increased by two times compared to the conventional counterpart.

A n:n Negotiation Model in the Deal based on Emotional Agent (감성적 에이전트 기반의 n:n 상거래 협상 모델)

  • 원일용;고성범
    • Proceedings of the Korea Inteligent Information System Society Conference
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    • 2000.11a
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    • pp.169-177
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    • 2000
  • In general, the size of index set of the emotion-based control is smaller than that of the logic-based control. And thus, by using the concept of emotion we can control the behavior's patterns of multiple persons more softly from the global viewpoint. The principle just mentioned, we think, can be applied on fille general purpose system. In this paper we presented a n : n negotiation model in the deal based on emotional agent. Through the emotional layers of the agents we tried to show that the flexible control of the negotiation process is possible especially in case of dynamic environment.

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Study on Implementation of Hardware Simulation System for Verification of Digital Circuit (디지털 회로 검증을 위한 하드웨어 시뮬레이션 시스템 구현에 관한 연구)

  • Cho, Hyun-Seob;Oh, Myoung-Kwan
    • Proceedings of the KAIS Fall Conference
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    • 2007.11a
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    • pp.78-80
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    • 2007
  • According to the development of VLSI integration technology and getting bigger the circuit size, it is a significant problem to verify systemized circuit. The faster and more accurate verification has very significant meaning in the field of electronic industry because it can yield the product comparably faster and reduce the trial and errors. In spite of the presence of various kind of Integrated Circuits it's not always easy to get the right part. Besides, it is hard to find a vendor for a small quantity consumers like who develop prototype applications. In this study, we've tried to get the logical signals from the PC based device we've developed that correspondents with the real ICs. It can emulate decoder ICs, multiplexers, demultiplexers and basic logic gates.

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Optimization Model for Planning of Experiments in Test and Evaluation Process (시험평가 실험계획을 위한 최적화 모형)

  • Cho, Namsuk
    • Journal of Applied Reliability
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    • v.18 no.2
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    • pp.173-183
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    • 2018
  • Purpose: It is critical to design a set of experiments in Test and Evaluation Process for a weapon system. Because there is no sufficient resources in real-world, one must choose a subset of experiments which is considered to be more important. Methods: We introduce an optimization model for choosing the subset of experiments by considering a priority of experimental variable and level and restrictions of resources. We describe in detail how we construct objective function and constraints which must be a right realization of our logic and assumption. Conclusion: Since our optimization model turns out to be computationally difficult to solve, we introduce an algorithm for reducing the size of problem. Various computational results follows.

Virtual Prototyping of Area-Based Fast Image Stitching Algorithm

  • Mudragada, Lakshmi Kalyani;Lee, Kye-Shin;Kim, Byung-Gyu
    • Journal of Multimedia Information System
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    • v.6 no.1
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    • pp.7-14
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    • 2019
  • This work presents a virtual prototyping design approach for an area-based image stitching hardware. The virtual hardware obtained from virtual prototyping is equivalent to the conceptual algorithm, yet the conceptual blocks are linked to the actual circuit components including the memory, logic gates, and arithmetic units. Through the proposed method, the overall structure, size, and computation speed of the actual hardware can be estimated in the early design stage. As a result, the optimized virtual hardware facilitates the hardware implementation by eliminating trail design and redundant simulation steps to optimize the hardware performance. In order to verify the feasibility of the proposed method, the virtual hardware of an image stitching platform has been realized, where it required 10,522,368 clock cycles to stitch two $1280{\times}1024$ sized images. Furthermore, with a clock frequency of 250MHz, the estimated computation time of the proposed virtual hardware is 0.877sec, which is 10x faster than the software-based image stitch platform using MATLAB.

Development of an Adaptive Neuro-Fuzzy Techniques based PD-Model for the Insulation Condition Monitoring and Diagnosis

  • Kim, Y.J.;Lim, J.S.;Park, D.H.;Cho, K.B.
    • Electrical & Electronic Materials
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    • v.11 no.11
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    • pp.1-8
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    • 1998
  • This paper presents an arificial neuro-fuzzy technique based prtial discharge (PD) pattern classifier to power system application. This may require a complicated analysis method employ -ing an experts system due to very complex progressing discharge form under exter-nal stress. After referring briefly to the developments of artificical neural network based PD measurements, the paper outlines how the introduction of new emerging technology has resulted in the design of a number of PD diagnostic systems for practical applicaton of residual lifetime prediction. The appropriate PD data base structure and selection of learning data size of PD pattern based on fractal dimentsional and 3-D PD-normalization, extraction of relevant characteristic fea-ture of PD recognition are discussed. Some practical aspects encountered with unknown stress in the neuro-fuzzy techniques based real time PD recognition are also addressed.

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