• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.209-218
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• 2012

Recently, the Field Programmable Stateful Logic Array (FPSLA) was proposed as one of the most promising system integration technologies which will extend the life of the Moore's law. This work is the first proposal of the FPSLA design automation flow, and the approaches to logic synthesis, synchronization, physical mapping, and automatic placement of the FPSLA designs. The synchronization at each gate for pipelining determines the x-coordinates of cells, and reduces the placement to 1-dimensional problems. The objective function and its gradients for the non-linear optimization of the net length and placement density have been remodeled for the reduced global placement problem. Also, a recursive algorithm has been proposed to legalize the placement by relaxing the density overflow of bipartite bin groups in a top-down hierarchical fashion. The proposed model and algorithm are implemented, and validated by applying them to the ACM/SIGDA benchmark designs. The output state of a gate in an FPSLA needs to be duplicated so that each fanout gate can be connected to a dedicated copy. This property has been taken into account by merging the duplicated nets into a hyperedge, and then, splitting the hyperedge into edges as the optimization progresses. This yields additional 18.4% of the cell count reduction in the most dense logic stage. The practicality of the FPSLA can be further enhanced primarily by incorporating into the logic synthesis the constraint to avoid the concentrated fains of gates on some logic stages. In addition, an efficient algorithm needs to be devised for the routing problem which is based on a complicated graph. The graph models the nanowire crossbar which is trimmed to be embedded into the FPSLA fabric, and therefore, asymmetric. These CAD tools can be used to evaluate the fabric efficiency during the architecture enhancement as well as automate the design.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1131-1150
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• 2014

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

• 한국가스학회:학술대회논문집
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• 1999.09a
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• pp.244-249
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• 1999

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1999.04a
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• pp.295-295
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• 1999

• Journal of the Korean Institute of Telematics and Electronics T
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• v.36T no.3
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• pp.94-100
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• 1999

In this paper, we are implemented the courseware targets to the integrated a digital system analysis, a design theory, and a hardware description language training and a logic analysis. This paper consists of two subjects. One is that the learning of a digital system analysis, that of a design theory, and the training of a hardware description language is simultaneously performed. The other is that the experiment of courseware. To learn the hardware description language, the explanation using sound or moving images, setting-up of a simulation or a synthesis program, and simulating are executed on a courseware. And also, we proposed an integrated systems for the hardware description language and a logic synthesis. Also, The reliablity of the tool was verified to be preyed an efficient operation of an implemented digital system courseware tool by korea computer research association.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10a
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• pp.238-242
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• 1991

This paper presents an approach to self-tuning PI control of dynamic plants, based on fuzzy logic application. A fuzzy logic composed of linguistic conditional statements is employed by defining the relations of input-output variables of the controller. In the synthesis of a fuzzy logic controller, one of the most difficult problem is the selection of linguistic control rules and parameters. To overcome this difficulty, self-tuning fuzzy PI controller (STFPIC) with a hierarchical structure in which the fuzzy PI controller is assigned as the lower level and the rule modification and parameter adjustment as the higher level. The rules and parameters are generated by the adjustment of membership function through performance index(PE). In this paper, the algorithm for of the controller performance is estimated by means of computer simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.7
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• pp.3251-3257
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• 2011

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts kernel-kernel pairs as well as cokernel-kernel pairs. The given logic expressions can be translated into Boolean divisors and quotients with kernel-kernel pairs. Next, kernel intersection method provides the common sub-expressions for several logic expressions. Experimental results show the improvement in literal count over previous other extraction methods.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.