• Health Policy and Management
• /
• v.32 no.3
• /
• pp.272-281
• /
• 2022

With the outbreak of coronavirus disease 2019 (COVID-19) pandemic, health policymakers are adopting new policies regarding the issue of immunization disparities, especially for children in low-income communities of color who lack awareness and thereby access to vaccines. The purpose of this paper is to propose an evaluation framework using program theory-based evaluation approach and logic model to analyze and evaluate the immunization disparities in children aged 19-35 months. Data is collected from New York City department of Health and the U.S. Census Bureau for Northern Manhattan Start Right Coalition program which consists of 19,800 children, and the community-provider partnership includes 26 practices and 20 groups. Program theory is used to evaluate this community-based initiative with the logic model which is a visual depiction that illustrations the program theory to all stakeholders. The logic model highlights the resources, activities, outputs, outcomes, and impacts of the program to guide to planners and evaluators and to call attention to the inadequacies or flaws in the operational, implementation and service delivery process of the program in offering a new perspective on the program. This framework adds to the literature on evaluations of immunization disparities in determining whether evaluators can definitively attribute positive immunization outcomes in the community to the program and conclude whether it has potential in expanding or duplicating it to other similar settings, especially in other rural areas of the United States, and abroad, where routine immunization equity gaps are wide due to income, racial and ethnic diversity, and language barrier.

• 제어로봇시스템학회:학술대회논문집
• /
• 1991.10a
• /
• pp.1110-1115
• /
• 1991

Tne mathematical modeling and analysis results of a dataflow logic solving processor(DFLSP) for programmable logic controller(PLC) are proposed in this paper. The logic program language is formalized using a dataflow graph model. From this dataflow graph, the instruction precedence relationship, and deadlock problems, which are major properties of a logic program, are described.

• Korean Journal of Logic
• /
• v.13 no.2
• /
• pp.27-59
• /
• 2010

After the unexpected death of the late professor Young-Jung Kim on July 28th last year, 4 pieces of paper unpublished were discovered. Those papers reveal that he had a grand program. In particular, we found that he had his own ideas and theory which he called "Presupposition Logic" and "Field Logic". In this paper, I will call his program "Presupposition Logic Program". He explored a new logic system, Presupposition Logic, in order to realize necessity and possibility of the closer relationship between logic and critical thinking. In this paper, I will expound what his "presupposition" and "Presupposition Logic" are and why he thought Presupposition Logic is necessary from a perspective of logic. And I will critically elucidate what was the problem that troubled him.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.12
• /
• pp.953-958
• /
• 2001

The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

• 제어로봇시스템학회:학술대회논문집
• /
• 1990.10a
• /
• pp.634-638
• /
• 1990

In this paper, the architecture of a dataflow logic solving processor for programmable logic controller is proposed. As the proposed DFLSP (dataflow logic solving processor) is designed based on the dataflow architecture, it has inherently concurrent processing and data synchronization capabilities. The proposed DFLSP is adequate for high speed programmable logic controllers and gets rid of data synchronization problem in hardware level. The performance of the proposed DFLSP is analyzed using computer simulations and prototype hardware. With single processing element, the logic solving time is 144 usec per 1K steps of logic program and with eight processing elements, the logic solving time is 23 usec per 1K steps of logic program with reasonable assumptions.

• Journal of Fisheries and Marine Sciences Education
• /
• v.28 no.2
• /
• pp.336-349
• /
• 2016

The evaluation of the after-school program depends on whether it achieves its objectives or not so far which makes that it is not easy to figure out which mechanism is attributed to the consequences of the program. This study aims at developing the logic model of the after-school program and follows the processes such as literature review, opinion survey by specialists and in-depth interview with stakeholders. The target program of the study was focused on the special ability aptitude education in the elementary schools. The initial developed theory model was validated and finalized through being reviewed by specialists and teachers in charge of target schools. Based on the framework of logic model, the models are composed of context, components, activities, output/short term outcomes, and long term outcomes. As the key factors of the after-school program, amicable communication between the stakeholders, quality of the program in itself, follow-up management, counseling and guidance for students, instructors' expertise, and quality management of the program were drawn.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.33 no.4
• /
• pp.134-139
• /
• 1984

This paper presents the computer program to design the synchronous sequential logic circuit. The computer program uses the MASK method to get the circuit of optimal cost. The computer program takes as an input, the minimal reduced state transition table where each state has its internal code. As an output,the optimal design of synchronous sequential logic circuit is generated for each flipflop type of JK,T,D, and RS respectively. And these circuits for 4 flipflop types are evaluated and sorted in ascending order of their costs, so that the user can select the proper flipflop type and its circuit. Furthermore,the proposed computer program may be applied to state assignment with its facility of cost evaluation.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2004.05a
• /
• pp.377-380
• /
• 2004

본 논문에서 우리는 지능형 e-비즈니스를 효과적으로 수행하기 위한 시맨틱 웹 서비스 아키텍처의 구성요소인 마크업인 OWL-S를 CLP(Constraint Logic Program) RuleML로의 확장 및 통합방안에 관한 연구결과를 제시한다. 우리의 주 공헌은 OLP(Ordinary Logic Program), SCLP(Situated Courteous Logic Program) 및 CLP(Constraint Logic Program) 사이의 표현력과 계산력을 비교 및 분석한 근거를 바탕으로 하여 시맨틱 웹, 웹 서비스 그리고 규칙표현 모두가 함께 사용될 수 있는 근거를 제공하였다는 것이다. 본 논문에서 제안된 접근법은 온톨로지를 마크업하기 위한 노력과 규칙을 표현하기 위한 노력이 자연스러운 방법으로 통합될 수 있는 근간을 마련할 뿐만 아니라 규칙들을 이용하여 온톨로지들을 보완하고, 규칙들에서 사용되는 용어들을 온톨로지들에서 정의된 용어들 및 속성들로 표현할 수 있다는 장점을 가진다.

• The Transactions of the Korean Institute of Electrical Engineers A
• /
• v.48 no.12
• /
• pp.1554-1563
• /
• 1999

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.