• Journal of Practical Engineering Education
• /
• v.9 no.1
• /
• pp.41-48
• /
• 2017

In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.148-151
• /
• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Progress in Superconductivity
• /
• v.9 no.2
• /
• pp.157-161
• /
• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.11
• /
• pp.1-10
• /
• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Journal of The Korean Association of Information Education
• /
• v.13 no.3
• /
• pp.341-349
• /
• 2009

In this paper, we proposed an Electric Circuit manipulation method to identify easily results of Digital Logic Circuits. Using this method for computer science educations, we can feasibly instruct and understand principles of a Digital Logic Circuit which is a basis of real Digital systems. Furthermore, we developed an PBL-based education program for Digital Logic Circuit concept and Boolean Algebra concept by applying the proposed Electric Circuit manipulation method and by explaining real life Digital Instrument examples. The experimental results are analyzed in views of the problem-solving ability and suitability of allocating degrees of difficulties to the developed Digital Logic Circuit problems.

• Journal of Practical Engineering Education
• /
• v.8 no.2
• /
• pp.95-101
• /
• 2016

In this paper, we introduce an implementation method of switch-based LED (Light Emitting Diode) Art logic circuits to help understanding the operation principle of digital logic circuits. Digital logic circuit practice using bread board is widely practiced in colleges or high schools in South Korea. However, actual digital logic circuit practice lacks examples of basic implementation, and as results of this problem, study with more complicated examples disturbs understanding the basic operation principle of digital logic circuits. Therefore, we proposed and tested an implementation method of switch-based LED Art logic circuits to help understanding the necessity of digital logic circuits which control signals of multiple output devices simultaneously.

• The Journal of Korean Association of Computer Education
• /
• v.11 no.2
• /
• pp.65-78
• /
• 2008

Many digital logic circuit simulators have been developed for the education on the experiments of digital logic circuits for college or high school students. But the existing simulators have some constraints on the number of inputs of gate, on the display of gate and wire states, and on the number of logic diagrams to be simulated. 1n this paper, we propose a simulator XSIM(eXpandable digital logic circuit SIMulator) which mitigates the constraints and allows multiple diagrams for large scale logics. It is expected that the multiple diagrams on large logics are helpful for team-teaching in school.

• Journal of IKEEE
• /
• v.12 no.4
• /
• pp.211-216
• /
• 2008

This paper proposes an 8${\times}$8 bit parallel multiplier using MOS current-mode logic (MCML) circuit for low power consumption. The proposed circuit has a structure of low-power MOS current-mode logic circuit with sleep-transistor to reduce the leakage current. The sleep-transistor is used to PMOS transistor to minimize the leakage current. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/50. The designed multiplier is achieved to reduce the power consumption by 10.5% and the power-delay-product by 11.6% compared with the conventional MOS current-model logic circuit. This circuit is designed with Samsung 0.35 ${\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• 제어로봇시스템학회:학술대회논문집
• /
• 1993.10b
• /
• pp.24-29
• /
• 1993

In this paper, the estimation of the structure of a logic circuit under test is made from the observation of the input-output correlation function by use of M-sequence, from which we can estimate whether or not any fault exist in the logic circuit. Especially, investigation was made in case of the 2_stage logic circuit. We checked theoretically the sequence of correlation function, and we have shown that the correlation function is a function of period of M-sequence only, land the appearing number of correlation function in a period is a constant value depending on the logic circuit only. And by computer simulations we have shown that the structure of the circuit under test can be estimated from the observation of sequence of correlation function.

• Journal of the Korea Society for Simulation
• /
• v.3 no.1
• /
• pp.107-114
• /
• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.